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-rw-r--r--fesvr/dtm.cc4
-rw-r--r--riscv/debug_module.cc12
-rw-r--r--riscv/encoding.h30
-rw-r--r--riscv/processor.cc8
4 files changed, 40 insertions, 14 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc
index 993011d..91cacb2 100644
--- a/fesvr/dtm.cc
+++ b/fesvr/dtm.cc
@@ -433,11 +433,11 @@ uint64_t dtm_t::modify_csr(unsigned which, uint64_t data, uint32_t type)
// need to run more commands to save and restore
// S0.
uint32_t prog[] = {
- CSRRx(WRITE, S0, CSR_DSCRATCH, S0),
+ CSRRx(WRITE, S0, CSR_DSCRATCH0, S0),
LOAD(xlen, S0, X0, data_base),
CSRRx(type, S0, which, S0),
STORE(xlen, S0, X0, data_base),
- CSRRx(WRITE, S0, CSR_DSCRATCH, S0),
+ CSRRx(WRITE, S0, CSR_DSCRATCH0, S0),
EBREAK
};
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 5c7d2f1..8ace1b9 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -590,10 +590,10 @@ bool debug_module_t::perform_abstract_command()
if (is_fpu_reg(regno)) {
// Save S0
- write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH));
+ write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0));
// Save mstatus
write32(debug_abstract, i++, csrr(S0, CSR_MSTATUS));
- write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH + 1));
+ write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH1));
// Set mstatus.fs
assert((MSTATUS_FS & 0xfff) == 0);
write32(debug_abstract, i++, lui(S0, MSTATUS_FS >> 12));
@@ -602,7 +602,7 @@ bool debug_module_t::perform_abstract_command()
if (regno < 0x1000 && config.support_abstract_csr_access) {
if (!is_fpu_reg(regno)) {
- write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH));
+ write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0));
}
if (write) {
@@ -634,7 +634,7 @@ bool debug_module_t::perform_abstract_command()
}
}
if (!is_fpu_reg(regno)) {
- write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH));
+ write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0));
}
} else if (regno >= 0x1000 && regno < 0x1020) {
@@ -709,10 +709,10 @@ bool debug_module_t::perform_abstract_command()
if (is_fpu_reg(regno)) {
// restore mstatus
- write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH + 1));
+ write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH1));
write32(debug_abstract, i++, csrw(S0, CSR_MSTATUS));
// restore s0
- write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH));
+ write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0));
}
}
diff --git a/riscv/encoding.h b/riscv/encoding.h
index e52a65a..371457f 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -1633,8 +1633,16 @@
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
#define CSR_HIDELEG 0x603
+#define CSR_HIE 0x604
+#define CSR_HTIMEDELTA 0x605
#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
+#define CSR_HTVAL 0x643
+#define CSR_HIP 0x644
+#define CSR_HVIP 0x645
+#define CSR_HTINST 0x64a
#define CSR_HGATP 0x680
+#define CSR_HGEIP 0xe12
#define CSR_UTVT 0x7
#define CSR_UNXTI 0x45
#define CSR_UINTSTATUS 0x46
@@ -1663,6 +1671,8 @@
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+#define CSR_MTINST 0x34a
+#define CSR_MTVAL2 0x34b
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@@ -1689,7 +1699,8 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MHPMCOUNTER3 0xb03
@@ -1754,6 +1765,7 @@
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+#define CSR_HTIMEDELTAH 0x615
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
@@ -1786,6 +1798,7 @@
#define CSR_HPMCOUNTER29H 0xc9d
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MSTATUSH 0x310
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
#define CSR_MHPMCOUNTER3H 0xb83
@@ -2572,8 +2585,16 @@ DECLARE_CSR(vsatp, CSR_VSATP)
DECLARE_CSR(hstatus, CSR_HSTATUS)
DECLARE_CSR(hedeleg, CSR_HEDELEG)
DECLARE_CSR(hideleg, CSR_HIDELEG)
+DECLARE_CSR(hie, CSR_HIE)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(htval, CSR_HTVAL)
+DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(htinst, CSR_HTINST)
DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(hgeip, CSR_HGEIP)
DECLARE_CSR(utvt, CSR_UTVT)
DECLARE_CSR(unxti, CSR_UNXTI)
DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
@@ -2602,6 +2623,8 @@ DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mtval, CSR_MTVAL)
DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(mtinst, CSR_MTINST)
+DECLARE_CSR(mtval2, CSR_MTVAL2)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
@@ -2628,7 +2651,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2)
DECLARE_CSR(tdata3, CSR_TDATA3)
DECLARE_CSR(dcsr, CSR_DCSR)
DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
DECLARE_CSR(mcycle, CSR_MCYCLE)
DECLARE_CSR(minstret, CSR_MINSTRET)
DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
@@ -2693,6 +2717,7 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID)
DECLARE_CSR(marchid, CSR_MARCHID)
DECLARE_CSR(mimpid, CSR_MIMPID)
DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
DECLARE_CSR(cycleh, CSR_CYCLEH)
DECLARE_CSR(timeh, CSR_TIMEH)
DECLARE_CSR(instreth, CSR_INSTRETH)
@@ -2725,6 +2750,7 @@ DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
DECLARE_CSR(mcycleh, CSR_MCYCLEH)
DECLARE_CSR(minstreth, CSR_MINSTRETH)
DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index d0fae14..4810297 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -802,10 +802,10 @@ void processor_t::set_csr(int which, reg_t val)
case CSR_DPC:
state.dpc = val & ~(reg_t)1;
break;
- case CSR_DSCRATCH:
+ case CSR_DSCRATCH0:
state.dscratch0 = val;
break;
- case CSR_DSCRATCH + 1:
+ case CSR_DSCRATCH1:
state.dscratch1 = val;
break;
case CSR_VSTART:
@@ -1002,11 +1002,11 @@ reg_t processor_t::get_csr(int which)
if (!state.debug_mode)
break;
return state.dpc & pc_alignment_mask();
- case CSR_DSCRATCH:
+ case CSR_DSCRATCH0:
if (!state.debug_mode)
break;
return state.dscratch0;
- case CSR_DSCRATCH + 1:
+ case CSR_DSCRATCH1:
if (!state.debug_mode)
break;
return state.dscratch1;
generated by cgit v1.1 at 2024-11-18 07:05:26 +0000