diff options
| -rw-r--r-- | riscv/csrs.cc | 9 | ||||
| -rw-r--r-- | riscv/csrs.h | 8 | ||||
| -rw-r--r-- | riscv/processor.cc | 19 | ||||
| -rw-r--r-- | riscv/processor.h | 2 |
4 files changed, 24 insertions, 14 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index f4849ea..ca277ad 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -952,3 +952,12 @@ bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept { mask &= ~(reg_t)3; return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } + + +tselect_csr_t::tselect_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool tselect_csr_t::unlogged_write(const reg_t val) noexcept { + return basic_csr_t::unlogged_write((val < state->num_triggers) ? val : read()); +} diff --git a/riscv/csrs.h b/riscv/csrs.h index 6f95f84..82e1709 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -500,4 +500,12 @@ class hgatp_csr_t: public basic_csr_t { }; +class tselect_csr_t: public basic_csr_t { + public: + tselect_csr_t(processor_t* const proc, const reg_t addr); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + + #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index 2c3b243..d3f53e1 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -501,7 +501,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) dscratch1 = 0; memset(&this->dcsr, 0, sizeof(this->dcsr)); - tselect = 0; + csrmap[CSR_TSELECT] = tselect = std::make_shared<tselect_csr_t>(proc, CSR_TSELECT); memset(this->mcontrol, 0, sizeof(this->mcontrol)); for (auto &item : mcontrol) item.type = 2; @@ -993,14 +993,9 @@ void processor_t::set_csr(int which, reg_t val) VU.vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; VU.vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; break; - case CSR_TSELECT: - if (val < state.num_triggers) { - state.tselect = val; - } - break; case CSR_TDATA1: { - mcontrol_t *mc = &state.mcontrol[state.tselect]; + mcontrol_t *mc = &state.mcontrol[state.tselect->read()]; if (mc->dmode && !state.debug_mode) { break; } @@ -1024,10 +1019,10 @@ void processor_t::set_csr(int which, reg_t val) } break; case CSR_TDATA2: - if (state.mcontrol[state.tselect].dmode && !state.debug_mode) { + if (state.mcontrol[state.tselect->read()].dmode && !state.debug_mode) { break; } - state.tdata2[state.tselect] = val; + state.tdata2[state.tselect->read()] = val; break; case CSR_DCSR: state.dcsr.prv = get_field(val, DCSR_PRV); @@ -1091,7 +1086,6 @@ void processor_t::set_csr(int which, reg_t val) LOG_CSR(CSR_VXRM); break; - case CSR_TSELECT: case CSR_TDATA1: case CSR_TDATA2: case CSR_DCSR: @@ -1160,11 +1154,10 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) case CSR_MIMPID: ret(0); case CSR_MVENDORID: ret(0); case CSR_MHARTID: ret(id); - case CSR_TSELECT: ret(state.tselect); case CSR_TDATA1: { reg_t v = 0; - mcontrol_t *mc = &state.mcontrol[state.tselect]; + mcontrol_t *mc = &state.mcontrol[state.tselect->read()]; v = set_field(v, MCONTROL_TYPE(xlen), mc->type); v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); @@ -1182,7 +1175,7 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) v = set_field(v, MCONTROL_LOAD, mc->load); ret(v); } - case CSR_TDATA2: ret(state.tdata2[state.tselect]); + case CSR_TDATA2: ret(state.tdata2[state.tselect->read()]); case CSR_TDATA3: ret(0); case CSR_DCSR: { diff --git a/riscv/processor.h b/riscv/processor.h index d1737c5..7ffca95 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -204,7 +204,7 @@ struct state_t reg_t dpc; reg_t dscratch0, dscratch1; dcsr_t dcsr; - reg_t tselect; + csr_t_p tselect; mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; bool debug_mode; |