diff options
| -rw-r--r-- | riscv/mmu.cc | 7 | ||||
| -rw-r--r-- | riscv/mmu.h | 5 |
2 files changed, 12 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 0dbb94e..3048bde 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -141,6 +141,13 @@ bool mmu_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) { + if (!matched_trigger) { + reg_t data = reg_from_bytes(len, bytes); + matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, false); + if (matched_trigger) + throw *matched_trigger; + } + reg_t paddr = translate(addr, len, LOAD, xlate_flags); if (auto host_addr = sim->addr_to_mem(paddr)) { diff --git a/riscv/mmu.h b/riscv/mmu.h index d076aeb..3a06c1e 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -101,6 +101,11 @@ public: #define load_func(type, prefix, xlate_flags) \ type##_t ALWAYS_INLINE prefix##_##type(reg_t addr, bool require_alignment = false) { \ if (unlikely(addr & (sizeof(type##_t)-1))) { \ + if (!matched_trigger) { \ + matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, false); \ + if (matched_trigger) \ + throw *matched_trigger; \ + } \ if (require_alignment) load_reserved_address_misaligned(addr); \ else return misaligned_load(addr, sizeof(type##_t), xlate_flags); \ } \ |