diff options
| -rw-r--r-- | riscv/decode.h | 4 | ||||
| -rw-r--r-- | riscv/execute.cc | 14 | ||||
| -rw-r--r-- | riscv/gdbserver.cc | 12 | ||||
| -rw-r--r-- | riscv/processor.cc | 22 | ||||
| -rw-r--r-- | riscv/processor.h | 10 | ||||
| -rw-r--r-- | riscv/sim.cc | 2 |
6 files changed, 24 insertions, 40 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index b922e02..784c717 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -229,5 +229,9 @@ private: * automatically generated. */ /* TODO */ #include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HALT 5 + +#define DEBUG_ROM_ENTRY 0x800 #endif diff --git a/riscv/execute.cc b/riscv/execute.cc index c36cb4f..8b8c902 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -53,14 +53,7 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) // fetch/decode/execute loop void processor_t::step(size_t n) { - // TODO: We should really not call this function at all when halted, to avoid - // burning CPU. - if (single_step) { - set_halted(false, HR_NONE); - n = 1; - } - - while (run && !halted && n > 0) { + while (n > 0) { size_t instret = 0; reg_t pc = state.pc; mmu_t* _mmu = mmu; @@ -133,9 +126,4 @@ miss: state.minstret += instret; n -= instret; } - - if (single_step) { - single_step = false; - set_halted(true, HR_STEPPED); - } } diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 0ab1aef..0fe5365 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -141,7 +141,7 @@ void gdbserver_t::accept() // gdb wants the core to be halted when it attaches. processor_t *p = sim->get_core(0); - p->set_halted(true, HR_ATTACHED); + // TODO p->set_halted(true, HR_ATTACHED); } } @@ -164,7 +164,7 @@ void gdbserver_t::read() // The remote disconnected. client_fd = 0; processor_t *p = sim->get_core(0); - p->set_halted(false, HR_NONE); + // TODO p->set_halted(false, HR_NONE); recv_buf.reset(); send_buf.reset(); } else { @@ -514,7 +514,7 @@ void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet) return send_packet("E30"); } - p->set_halted(false, HR_NONE); + // TODO p->set_halted(false, HR_NONE); running = true; } @@ -529,7 +529,7 @@ void gdbserver_t::handle_step(const std::vector<uint8_t> &packet) return send_packet("E40"); } - p->set_single_step(true); + // TODO: p->set_single_step(true); running = true; } @@ -693,7 +693,7 @@ void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet) void gdbserver_t::handle_interrupt() { processor_t *p = sim->get_core(0); - p->set_halted(true, HR_INTERRUPT); + // TODO p->set_halted(true, HR_INTERRUPT); send_packet("S02"); // Pretend program received SIGINT. running = false; } @@ -702,6 +702,7 @@ void gdbserver_t::handle() { if (client_fd > 0) { processor_t *p = sim->get_core(0); + /* TODO if (running && p->halted) { // The core was running, but now it's halted. Better tell gdb. switch (p->halt_reason) { @@ -723,6 +724,7 @@ void gdbserver_t::handle() // TODO: Actually include register values here running = false; } + */ this->read(); this->write(); diff --git a/riscv/processor.cc b/riscv/processor.cc index 996f9e3..df9a724 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -22,7 +22,7 @@ processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id) : sim(sim), ext(NULL), disassembler(new disassembler_t), - id(id), run(false), debug(false), halted(false), single_step(false) + id(id), run(false), debug(false) { parse_isa_string(isa); @@ -126,17 +126,6 @@ void processor_t::set_debug(bool value) ext->set_debug(value); } -void processor_t::set_halted(bool value, halt_reason_t reason) -{ - halted = value; - halt_reason = reason; -} - -void processor_t::set_single_step(bool value) -{ - single_step = value; -} - void processor_t::set_histogram(bool value) { histogram_enabled = value; @@ -203,6 +192,13 @@ void processor_t::set_privilege(reg_t prv) state.prv = prv; } +void processor_t::enter_debug_mode(uint8_t cause) +{ + state.dcsr.cause = cause; + state.dpc = state.pc; + state.pc = DEBUG_ROM_ENTRY; +} + void processor_t::take_trap(trap_t& t, reg_t epc) { if (debug) @@ -211,7 +207,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (t.cause() == CAUSE_BREAKPOINT && sim->gdbserver && sim->gdbserver->connected()) { - set_halted(true, HR_SWBP); + enter_debug_mode(DCSR_CAUSE_SWBP); return; } diff --git a/riscv/processor.h b/riscv/processor.h index e014299..8ac8507 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -107,8 +107,6 @@ public: ~processor_t(); void set_debug(bool value); - void set_halted(bool value, halt_reason_t reason); - void set_single_step(bool value); void set_histogram(bool value); void reset(bool value); void step(size_t n); // run for n cycles @@ -148,12 +146,6 @@ private: bool run; // !reset // When true, display disassembly of each instruction that's executed. bool debug; - // TODO: Should this just be rolled into `run`? - bool halted; // When true, no instructions are executed. - halt_reason_t halt_reason; // Why is halted true? - // When true, execute exactly one instruction (even if halted is true), then - // set halted to true and single_step to false. - bool single_step; bool histogram_enabled; std::vector<insn_desc_t> instructions; @@ -167,6 +159,8 @@ private: void take_trap(trap_t& t, reg_t epc); // take an exception void disasm(insn_t insn); // disassemble and print an instruction + void enter_debug_mode(uint8_t cause); + friend class sim_t; friend class mmu_t; friend class rtc_t; diff --git a/riscv/sim.cc b/riscv/sim.cc index ccaa6c8..095c2d9 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -45,7 +45,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, i); - procs[i]->set_halted(halted, HR_CMDLINE); + procs[i]->enter_debug_mode(DCSR_CAUSE_HALT); } rtc.reset(new rtc_t(procs)); |