diff options
| -rw-r--r-- | riscv/csrs.cc | 8 | ||||
| -rw-r--r-- | riscv/csrs.h | 2 |
2 files changed, 8 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 82a46ab..9673106 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -318,6 +318,10 @@ base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): } +bool base_status_csr_t::enabled(const reg_t which) { + return (read() & which) != 0; +} + reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { // If a configuration has FS bits, they will always be accessible no // matter the state of misa. @@ -474,9 +478,9 @@ void sstatus_csr_t::dirty(const reg_t dirties) { } bool sstatus_csr_t::enabled(const reg_t which) { - if ((orig_csr->read() & which) == 0) + if (!orig_sstatus->enabled(which)) return false; - if (state->v && ((virt_csr->read() & which) == 0)) + if (state->v && !virt_sstatus->enabled(which)) return false; return true; } diff --git a/riscv/csrs.h b/riscv/csrs.h index 3eb6bf5..bb53876 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -180,6 +180,8 @@ class cause_csr_t: public basic_csr_t { class base_status_csr_t: public csr_t { public: base_status_csr_t(processor_t* const proc, const reg_t addr); + // Return true if the specified bits are not 00 (Off) + bool enabled(const reg_t which); protected: reg_t adjust_sd(const reg_t val) const noexcept; void maybe_flush_tlb(const reg_t newval) noexcept; |