8 files changed, 19 insertions, 13 deletions

diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h
index 8ca7c41..b5d9e48 100644
--- a/riscv/insns/csrrc.h
+++ b/riscv/insns/csrrc.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) & ~RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) & ~RS1)));
diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index fc98056..6c63125 100644
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) & ~(reg_t)insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) & ~(reg_t)insn.rs1())));
diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index 60ac6b3..ba315d4 100644
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), insn.rs1() != 0);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) | RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | RS1)));
diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h
index db6fcd0..827d2d0 100644
--- a/riscv/insns/csrrsi.h
+++ b/riscv/insns/csrrsi.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, p->get_pcr(csr) | insn.rs1())));
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 4b16773..94793e2 100644
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, RS1)));
diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index ff20833..b8ec5f5 100644
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, insn.rs1())));
diff --git a/riscv/processor.cc b/riscv/processor.cc
index e931c6b..f47c8e5 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -32,6 +32,7 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
 
 processor_t::~processor_t()
 {
+  delete disassembler;
 }
 
 void state_t::reset()
@@ -232,12 +233,12 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case CSR_EVEC:
       state.evec = val & ~3;
       break;
-    case CSR_CYCLE:
-    case CSR_TIME:
-    case CSR_INSTRET:
     case CSR_COUNT:
       state.count = val;
       break;
+    case CSR_COUNTH:
+      state.count = (val << 32) | (uint32_t)state.count;
+      break;
     case CSR_COMPARE:
       set_interrupt(IRQ_TIMER, false);
       state.compare = val;
@@ -298,6 +299,13 @@ reg_t processor_t::get_pcr(int which)
     case CSR_INSTRET:
     case CSR_COUNT:
       return state.count;
+    case CSR_CYCLEH:
+    case CSR_TIMEH:
+    case CSR_INSTRETH:
+    case CSR_COUNTH:
+      if (rv64)
+        break;
+      return state.count >> 32;
     case CSR_COMPARE:
       return state.compare;
     case CSR_CAUSE:
@@ -326,9 +334,8 @@ reg_t processor_t::get_pcr(int which)
     case CSR_FROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
-    default:
-      throw trap_illegal_instruction();
   }
+  throw trap_illegal_instruction();
 }
 
 void processor_t::set_interrupt(int which, bool on)
diff --git a/riscv/processor.h b/riscv/processor.h
index 9e52d3d..e2847fa 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -5,7 +5,6 @@
 #include "decode.h"
 #include "config.h"
 #include <cstring>
-#include <memory>
 #include <vector>
 
 class processor_t;
@@ -80,7 +79,7 @@ private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
   extension_t* ext;
-  std::unique_ptr<disassembler_t> disassembler;
+  disassembler_t* disassembler;
   state_t state;
   uint32_t id;
   bool run; // !reset