diff options
| -rw-r--r-- | riscv/encoding.h | 72 | ||||
| -rw-r--r-- | riscv/insns/vnclip_wi.h (renamed from riscv/insns/vnclip_vi.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnclip_wv.h (renamed from riscv/insns/vnclip_vv.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnclip_wx.h (renamed from riscv/insns/vnclip_vx.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnclipu_wi.h (renamed from riscv/insns/vnclipu_vi.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnclipu_wv.h (renamed from riscv/insns/vnclipu_vv.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnclipu_wx.h (renamed from riscv/insns/vnclipu_vx.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsra_wi.h (renamed from riscv/insns/vnsra_vi.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsra_wv.h (renamed from riscv/insns/vnsra_vv.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsra_wx.h (renamed from riscv/insns/vnsra_vx.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsrl_wi.h (renamed from riscv/insns/vnsrl_vi.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsrl_wv.h (renamed from riscv/insns/vnsrl_vv.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/vnsrl_wx.h (renamed from riscv/insns/vnsrl_vx.h) | 0 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 24 | ||||
| -rw-r--r-- | spike_main/disasm.cc | 56 |
15 files changed, 78 insertions, 74 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 9ccb68c..ec4ad8e 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1120,14 +1120,14 @@ #define MASK_VSSRL_VX 0xfc00707f #define MATCH_VSSRA_VX 0xac004057 #define MASK_VSSRA_VX 0xfc00707f -#define MATCH_VNSRL_VX 0xb0004057 -#define MASK_VNSRL_VX 0xfc00707f -#define MATCH_VNSRA_VX 0xb4004057 -#define MASK_VNSRA_VX 0xfc00707f -#define MATCH_VNCLIPU_VX 0xb8004057 -#define MASK_VNCLIPU_VX 0xfc00707f -#define MATCH_VNCLIP_VX 0xbc004057 -#define MASK_VNCLIP_VX 0xfc00707f +#define MATCH_VNSRL_WX 0xb0004057 +#define MASK_VNSRL_WX 0xfc00707f +#define MATCH_VNSRA_WX 0xb4004057 +#define MASK_VNSRA_WX 0xfc00707f +#define MATCH_VNCLIPU_WX 0xb8004057 +#define MASK_VNCLIPU_WX 0xfc00707f +#define MATCH_VNCLIP_WX 0xbc004057 +#define MASK_VNCLIP_WX 0xfc00707f #define MATCH_VQMACCU_VX 0xf0004057 #define MASK_VQMACCU_VX 0xfc00707f #define MATCH_VQMACC_VX 0xf4004057 @@ -1200,14 +1200,14 @@ #define MASK_VSSRL_VV 0xfc00707f #define MATCH_VSSRA_VV 0xac000057 #define MASK_VSSRA_VV 0xfc00707f -#define MATCH_VNSRL_VV 0xb0000057 -#define MASK_VNSRL_VV 0xfc00707f -#define MATCH_VNSRA_VV 0xb4000057 -#define MASK_VNSRA_VV 0xfc00707f -#define MATCH_VNCLIPU_VV 0xb8000057 -#define MASK_VNCLIPU_VV 0xfc00707f -#define MATCH_VNCLIP_VV 0xbc000057 -#define MASK_VNCLIP_VV 0xfc00707f +#define MATCH_VNSRL_WV 0xb0000057 +#define MASK_VNSRL_WV 0xfc00707f +#define MATCH_VNSRA_WV 0xb4000057 +#define MASK_VNSRA_WV 0xfc00707f +#define MATCH_VNCLIPU_WV 0xb8000057 +#define MASK_VNCLIPU_WV 0xfc00707f +#define MATCH_VNCLIP_WV 0xbc000057 +#define MASK_VNCLIP_WV 0xfc00707f #define MATCH_VWREDSUMU_VS 0xc0000057 #define MASK_VWREDSUMU_VS 0xfc00707f #define MATCH_VWREDSUM_VS 0xc4000057 @@ -1272,14 +1272,14 @@ #define MASK_VSSRL_VI 0xfc00707f #define MATCH_VSSRA_VI 0xac003057 #define MASK_VSSRA_VI 0xfc00707f -#define MATCH_VNSRL_VI 0xb0003057 -#define MASK_VNSRL_VI 0xfc00707f -#define MATCH_VNSRA_VI 0xb4003057 -#define MASK_VNSRA_VI 0xfc00707f -#define MATCH_VNCLIPU_VI 0xb8003057 -#define MASK_VNCLIPU_VI 0xfc00707f -#define MATCH_VNCLIP_VI 0xbc003057 -#define MASK_VNCLIP_VI 0xfc00707f +#define MATCH_VNSRL_WI 0xb0003057 +#define MASK_VNSRL_WI 0xfc00707f +#define MATCH_VNSRA_WI 0xb4003057 +#define MASK_VNSRA_WI 0xfc00707f +#define MATCH_VNCLIPU_WI 0xb8003057 +#define MASK_VNCLIPU_WI 0xfc00707f +#define MATCH_VNCLIP_WI 0xbc003057 +#define MASK_VNCLIP_WI 0xfc00707f #define MATCH_VREDSUM_VS 0x2057 #define MASK_VREDSUM_VS 0xfc00707f #define MATCH_VREDAND_VS 0x4002057 @@ -2231,10 +2231,10 @@ DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) -DECLARE_INSN(vnsrl_vx, MATCH_VNSRL_VX, MASK_VNSRL_VX) -DECLARE_INSN(vnsra_vx, MATCH_VNSRA_VX, MASK_VNSRA_VX) -DECLARE_INSN(vnclipu_vx, MATCH_VNCLIPU_VX, MASK_VNCLIPU_VX) -DECLARE_INSN(vnclip_vx, MATCH_VNCLIP_VX, MASK_VNCLIP_VX) +DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) +DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) +DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) +DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX) DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX) DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX) @@ -2271,10 +2271,10 @@ DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) -DECLARE_INSN(vnsrl_vv, MATCH_VNSRL_VV, MASK_VNSRL_VV) -DECLARE_INSN(vnsra_vv, MATCH_VNSRA_VV, MASK_VNSRA_VV) -DECLARE_INSN(vnclipu_vv, MATCH_VNCLIPU_VV, MASK_VNCLIPU_VV) -DECLARE_INSN(vnclip_vv, MATCH_VNCLIP_VV, MASK_VNCLIP_VV) +DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) +DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) +DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) +DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) @@ -2307,10 +2307,10 @@ DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) -DECLARE_INSN(vnsrl_vi, MATCH_VNSRL_VI, MASK_VNSRL_VI) -DECLARE_INSN(vnsra_vi, MATCH_VNSRA_VI, MASK_VNSRA_VI) -DECLARE_INSN(vnclipu_vi, MATCH_VNCLIPU_VI, MASK_VNCLIPU_VI) -DECLARE_INSN(vnclip_vi, MATCH_VNCLIP_VI, MASK_VNCLIP_VI) +DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) +DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) +DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) +DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) diff --git a/riscv/insns/vnclip_vi.h b/riscv/insns/vnclip_wi.h index eb21710..eb21710 100644 --- a/riscv/insns/vnclip_vi.h +++ b/riscv/insns/vnclip_wi.h diff --git a/riscv/insns/vnclip_vv.h b/riscv/insns/vnclip_wv.h index 92575a6..92575a6 100644 --- a/riscv/insns/vnclip_vv.h +++ b/riscv/insns/vnclip_wv.h diff --git a/riscv/insns/vnclip_vx.h b/riscv/insns/vnclip_wx.h index 96409de..96409de 100644 --- a/riscv/insns/vnclip_vx.h +++ b/riscv/insns/vnclip_wx.h diff --git a/riscv/insns/vnclipu_vi.h b/riscv/insns/vnclipu_wi.h index b1527f7..b1527f7 100644 --- a/riscv/insns/vnclipu_vi.h +++ b/riscv/insns/vnclipu_wi.h diff --git a/riscv/insns/vnclipu_vv.h b/riscv/insns/vnclipu_wv.h index 217e82f..217e82f 100644 --- a/riscv/insns/vnclipu_vv.h +++ b/riscv/insns/vnclipu_wv.h diff --git a/riscv/insns/vnclipu_vx.h b/riscv/insns/vnclipu_wx.h index ce15b55..ce15b55 100644 --- a/riscv/insns/vnclipu_vx.h +++ b/riscv/insns/vnclipu_wx.h diff --git a/riscv/insns/vnsra_vi.h b/riscv/insns/vnsra_wi.h index f41979e..f41979e 100644 --- a/riscv/insns/vnsra_vi.h +++ b/riscv/insns/vnsra_wi.h diff --git a/riscv/insns/vnsra_vv.h b/riscv/insns/vnsra_wv.h index 59f255e..59f255e 100644 --- a/riscv/insns/vnsra_vv.h +++ b/riscv/insns/vnsra_wv.h diff --git a/riscv/insns/vnsra_vx.h b/riscv/insns/vnsra_wx.h index adaa24c..adaa24c 100644 --- a/riscv/insns/vnsra_vx.h +++ b/riscv/insns/vnsra_wx.h diff --git a/riscv/insns/vnsrl_vi.h b/riscv/insns/vnsrl_wi.h index 91402c0..91402c0 100644 --- a/riscv/insns/vnsrl_vi.h +++ b/riscv/insns/vnsrl_wi.h diff --git a/riscv/insns/vnsrl_vv.h b/riscv/insns/vnsrl_wv.h index 609299f..609299f 100644 --- a/riscv/insns/vnsrl_vv.h +++ b/riscv/insns/vnsrl_wv.h diff --git a/riscv/insns/vnsrl_vx.h b/riscv/insns/vnsrl_wx.h index 8356a2b..8356a2b 100644 --- a/riscv/insns/vnsrl_vx.h +++ b/riscv/insns/vnsrl_wx.h diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 463281c..e83602d 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -382,22 +382,22 @@ riscv_insn_ext_v_alu_int = \ vmv_x_s \ vmxnor_mm \ vmxor_mm \ - vnclip_vi \ - vnclip_vv \ - vnclip_vx \ - vnclipu_vi \ - vnclipu_vv \ - vnclipu_vx \ + vnclip_wi \ + vnclip_wv \ + vnclip_wx \ + vnclipu_wi \ + vnclipu_wv \ + vnclipu_wx \ vnmsac_vv \ vnmsac_vx \ vnmsub_vv \ vnmsub_vx \ - vnsra_vi \ - vnsra_vv \ - vnsra_vx \ - vnsrl_vi \ - vnsrl_vv \ - vnsrl_vx \ + vnsra_wi \ + vnsra_wv \ + vnsra_wx \ + vnsrl_wi \ + vnsrl_wv \ + vnsrl_wx \ vor_vi \ vor_vv \ vor_vx \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index a14ad96..373c6bb 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -805,17 +805,21 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("vl1r.v", vl1r_v, 0, {&vd, &v_address}); DISASM_INSN("vs1r.v", vs1r_v, 0, {&vs3, &v_address}); - #define DISASM_OPIV_VXI_INSN(name, sign) \ - add_insn(new disasm_insn_t(#name ".vv", match_##name##_vv, mask_##name##_vv, \ + #define DISASM_OPIV_VXI_INSN(name, sign, suf) \ + add_insn(new disasm_insn_t(#name "." #suf "v", \ + match_##name##_##suf##v, mask_##name##_##suf##v, \ {&vd, &vs2, &vs1, &opt, &vm})); \ - add_insn(new disasm_insn_t(#name ".vx", match_##name##_vx, mask_##name##_vx, \ + add_insn(new disasm_insn_t(#name "." #suf "x", \ + match_##name##_##suf##x, mask_##name##_##suf##x, \ {&vd, &vs2, &xrs1, &opt, &vm})); \ if (sign) \ - add_insn(new disasm_insn_t(#name ".vi", match_##name##_vi, mask_##name##_vi, \ + add_insn(new disasm_insn_t(#name "." #suf "i", \ + match_##name##_##suf##i, mask_##name##_##suf##i, \ {&vd, &vs2, &v_simm5, &opt, &vm})); \ else \ - add_insn(new disasm_insn_t(#name ".vi", match_##name##_vi, mask_##name##_vi, \ - {&vd, &vs2, &zimm5, &opt, &vm})); + add_insn(new disasm_insn_t(#name "." #suf "i", \ + match_##name##_##suf##i, mask_##name##_##suf##i, \ + {&vd, &vs2, &zimm5, &opt, &vm})); #define DISASM_OPIV_VX__INSN(name, sign) \ add_insn(new disasm_insn_t(#name ".vv", match_##name##_vv, mask_##name##_vv, \ @@ -869,17 +873,17 @@ disassembler_t::disassembler_t(int xlen) //OPFVV/OPFVF //0b00_0000 - DISASM_OPIV_VXI_INSN(vadd, 1); + DISASM_OPIV_VXI_INSN(vadd, 1, v); DISASM_OPIV_VX__INSN(vsub, 1); DISASM_OPIV__XI_INSN(vrsub, 1); DISASM_OPIV_VX__INSN(vminu, 0); DISASM_OPIV_VX__INSN(vmin, 1); DISASM_OPIV_VX__INSN(vmaxu, 1); DISASM_OPIV_VX__INSN(vmax, 0); - DISASM_OPIV_VXI_INSN(vand, 1); - DISASM_OPIV_VXI_INSN(vor, 1); - DISASM_OPIV_VXI_INSN(vxor, 1); - DISASM_OPIV_VXI_INSN(vrgather, 0); + DISASM_OPIV_VXI_INSN(vand, 1, v); + DISASM_OPIV_VXI_INSN(vor, 1, v); + DISASM_OPIV_VXI_INSN(vxor, 1, v); + DISASM_OPIV_VXI_INSN(vrgather, 0, v); DISASM_OPIV__XI_INSN(vslideup, 1); DISASM_OPIV__XI_INSN(vslidedown,1); @@ -892,34 +896,34 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("vmv.v.i", vmv_v_i, 0, {&vd, &v_simm5}); DISASM_INSN("vmv.v.v", vmv_v_v, 0, {&vd, &vs1}); DISASM_INSN("vmv.v.x", vmv_v_x, 0, {&vd, &xrs1}); - DISASM_OPIV_VXI_INSN(vmseq, 1); - DISASM_OPIV_VXI_INSN(vmsne, 1); + DISASM_OPIV_VXI_INSN(vmseq, 1, v); + DISASM_OPIV_VXI_INSN(vmsne, 1, v); DISASM_OPIV_VX__INSN(vmsltu, 0); DISASM_OPIV_VX__INSN(vmslt, 1); - DISASM_OPIV_VXI_INSN(vmsleu, 0); - DISASM_OPIV_VXI_INSN(vmsle, 1); + DISASM_OPIV_VXI_INSN(vmsleu, 0, v); + DISASM_OPIV_VXI_INSN(vmsle, 1, v); DISASM_OPIV__XI_INSN(vmsgtu, 0); DISASM_OPIV__XI_INSN(vmsgt, 1); //0b10_0000 - DISASM_OPIV_VXI_INSN(vsaddu, 0); - DISASM_OPIV_VXI_INSN(vsadd, 1); + DISASM_OPIV_VXI_INSN(vsaddu, 0, v); + DISASM_OPIV_VXI_INSN(vsadd, 1, v); DISASM_OPIV_VX__INSN(vssubu, 0); DISASM_OPIV_VX__INSN(vssub, 1); - DISASM_OPIV_VXI_INSN(vsll, 1); + DISASM_OPIV_VXI_INSN(vsll, 1, v); DISASM_OPIV_VX__INSN(vaaddu, 0); DISASM_OPIV_VX__INSN(vaadd, 0); DISASM_OPIV_VX__INSN(vasubu, 0); DISASM_OPIV_VX__INSN(vasub, 0); DISASM_OPIV_VX__INSN(vsmul, 1); - DISASM_OPIV_VXI_INSN(vsrl, 0); - DISASM_OPIV_VXI_INSN(vsra, 0); - DISASM_OPIV_VXI_INSN(vssrl, 0); - DISASM_OPIV_VXI_INSN(vssra, 0); - DISASM_OPIV_VXI_INSN(vnsrl, 0); - DISASM_OPIV_VXI_INSN(vnsra, 0); - DISASM_OPIV_VXI_INSN(vnclipu, 0); - DISASM_OPIV_VXI_INSN(vnclip, 1); + DISASM_OPIV_VXI_INSN(vsrl, 0, v); + DISASM_OPIV_VXI_INSN(vsra, 0, v); + DISASM_OPIV_VXI_INSN(vssrl, 0, v); + DISASM_OPIV_VXI_INSN(vssra, 0, v); + DISASM_OPIV_VXI_INSN(vnsrl, 0, w); + DISASM_OPIV_VXI_INSN(vnsra, 0, w); + DISASM_OPIV_VXI_INSN(vnclipu, 0, w); + DISASM_OPIV_VXI_INSN(vnclip, 1, w); //0b11_0000 DISASM_OPIV_S___INSN(vwredsumu, 0); |