diff options
| -rw-r--r-- | riscv/csrs.cc | 63 | ||||
| -rw-r--r-- | riscv/csrs.h | 37 | ||||
| -rw-r--r-- | riscv/dts.cc | 2 | ||||
| -rw-r--r-- | riscv/entropy_source.h | 1 | ||||
| -rw-r--r-- | riscv/interactive.cc | 1 | ||||
| -rw-r--r-- | riscv/processor.h | 1 | ||||
| -rw-r--r-- | riscv/triggers.cc | 1 | ||||
| -rw-r--r-- | riscv/v_ext_macros.h | 4 |
8 files changed, 0 insertions, 110 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6bca99c..7d1be10 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -18,7 +18,6 @@ #undef STATE #define STATE (*state) - // implement class csr_t csr_t::csr_t(processor_t* const proc, const reg_t addr): proc(proc), @@ -47,7 +46,6 @@ void csr_t::verify_permissions(insn_t insn, bool write) const { } } - csr_t::~csr_t() { } @@ -83,7 +81,6 @@ bool basic_csr_t::unlogged_write(const reg_t val) noexcept { return true; } - // implement class pmpaddr_csr_t pmpaddr_csr_t::pmpaddr_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), @@ -92,7 +89,6 @@ pmpaddr_csr_t::pmpaddr_csr_t(processor_t* const proc, const reg_t addr): pmpidx(address - CSR_PMPADDR0) { } - void pmpaddr_csr_t::verify_permissions(insn_t insn, bool write) const { csr_t::verify_permissions(insn, write); // If n_pmp is zero, that means pmp is not implemented hence raise @@ -103,14 +99,12 @@ void pmpaddr_csr_t::verify_permissions(insn_t insn, bool write) const { throw trap_illegal_instruction(insn.bits()); } - reg_t pmpaddr_csr_t::read() const noexcept { if ((cfg & PMP_A) >= PMP_NAPOT) return val | (~proc->pmp_tor_mask() >> 1); return val & proc->pmp_tor_mask(); } - bool pmpaddr_csr_t::unlogged_write(const reg_t val) noexcept { // If no PMPs are configured, disallow access to all. Otherwise, // allow access to all, but unimplemented ones are hardwired to @@ -140,25 +134,21 @@ bool pmpaddr_csr_t::next_locked_and_tor() const noexcept { return next_locked && next_tor; } - reg_t pmpaddr_csr_t::tor_paddr() const noexcept { return (val & proc->pmp_tor_mask()) << PMP_SHIFT; } - reg_t pmpaddr_csr_t::tor_base_paddr() const noexcept { if (pmpidx == 0) return 0; // entry 0 always uses 0 as base return state->pmpaddr[pmpidx-1]->tor_paddr(); } - reg_t pmpaddr_csr_t::napot_mask() const noexcept { bool is_na4 = (cfg & PMP_A) == PMP_NA4; reg_t mask = (val << 1) | (!is_na4) | ~proc->pmp_tor_mask(); return ~(mask & ~(mask + 1)) << PMP_SHIFT; } - bool pmpaddr_csr_t::match4(reg_t addr) const noexcept { if ((cfg & PMP_A) == 0) return false; bool is_tor = (cfg & PMP_A) == PMP_TOR; @@ -167,7 +157,6 @@ bool pmpaddr_csr_t::match4(reg_t addr) const noexcept { return ((addr ^ tor_paddr()) & napot_mask()) == 0; } - bool pmpaddr_csr_t::subset_match(reg_t addr, reg_t len) const noexcept { if ((addr | len) & (len - 1)) abort(); @@ -190,7 +179,6 @@ bool pmpaddr_csr_t::subset_match(reg_t addr, reg_t len) const noexcept { return !(is_tor ? tor_homogeneous : napot_homogeneous); } - bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode) const noexcept { const bool cfgx = cfg & PMP_X; const bool cfgw = cfg & PMP_W; @@ -225,7 +213,6 @@ bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode) const noexcept { } } - // implement class pmpcfg_csr_t pmpcfg_csr_t::pmpcfg_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr) { @@ -328,7 +315,6 @@ virtualized_csr_t::virtualized_csr_t(processor_t* const proc, csr_t_p orig, csr_ virt_csr(virt) { } - reg_t virtualized_csr_t::read() const noexcept { return readvirt(state->v); } @@ -345,49 +331,41 @@ bool virtualized_csr_t::unlogged_write(const reg_t val) noexcept { return false; // virt_csr or orig_csr has already logged } - // implement class epc_csr_t epc_csr_t::epc_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), val(0) { } - reg_t epc_csr_t::read() const noexcept { return val & proc->pc_alignment_mask(); } - bool epc_csr_t::unlogged_write(const reg_t val) noexcept { this->val = val & ~(reg_t)1; return true; } - // implement class tvec_csr_t tvec_csr_t::tvec_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), val(0) { } - reg_t tvec_csr_t::read() const noexcept { return val; } - bool tvec_csr_t::unlogged_write(const reg_t val) noexcept { this->val = val & ~(reg_t)2; return true; } - // implement class cause_csr_t cause_csr_t::cause_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } - reg_t cause_csr_t::read() const noexcept { reg_t val = basic_csr_t::read(); // When reading, the interrupt bit needs to adjust to xlen. Spike does @@ -398,7 +376,6 @@ reg_t cause_csr_t::read() const noexcept { return val; } - // implement class base_status_csr_t base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), @@ -408,7 +385,6 @@ base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): | (proc->get_const_xlen() == 32 ? SSTATUS32_SD : SSTATUS64_SD)) { } - reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { // If a configuration has FS bits, they will always be accessible no // matter the state of misa. @@ -424,7 +400,6 @@ reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { ; } - reg_t base_status_csr_t::adjust_sd(const reg_t val) const noexcept { // This uses get_const_xlen() instead of get_xlen() not only because // the variable is static, so it's only called once, but also @@ -440,7 +415,6 @@ reg_t base_status_csr_t::adjust_sd(const reg_t val) const noexcept { return val & ~sd_bit; } - void base_status_csr_t::maybe_flush_tlb(const reg_t newval) noexcept { if ((newval ^ read()) & (MSTATUS_MPP | MSTATUS_MPRV @@ -449,7 +423,6 @@ void base_status_csr_t::maybe_flush_tlb(const reg_t newval) noexcept { proc->get_mmu()->flush_tlb(); } - namespace { int xlen_to_uxl(int xlen) { if (xlen == 32) @@ -460,7 +433,6 @@ namespace { } } - // implement class vsstatus_csr_t vsstatus_csr_t::vsstatus_csr_t(processor_t* const proc, const reg_t addr): base_status_csr_t(proc, addr), @@ -474,7 +446,6 @@ bool vsstatus_csr_t::unlogged_write(const reg_t val) noexcept { return true; } - // implement class sstatus_proxy_csr_t sstatus_proxy_csr_t::sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus): base_status_csr_t(proc, addr), @@ -488,7 +459,6 @@ bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept { return false; // avoid double logging: already logged by mstatus->write() } - // implement class mstatus_csr_t mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr): base_status_csr_t(proc, addr), @@ -503,7 +473,6 @@ mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr): ) { } - bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { const bool has_mpv = proc->extension_enabled('S') && proc->extension_enabled('H'); const bool has_gva = has_mpv; @@ -576,7 +545,6 @@ bool sstatus_csr_t::enabled(const reg_t which) { return false; } - // implement class misa_csr_t misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa): basic_csr_t(proc, addr, max_isa), @@ -637,7 +605,6 @@ bool misa_csr_t::extension_enabled_const(unsigned char ext) const noexcept { return extension_enabled(ext); } - // implement class mip_or_mie_csr_t mip_or_mie_csr_t::mip_or_mie_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), @@ -658,7 +625,6 @@ bool mip_or_mie_csr_t::unlogged_write(const reg_t val) noexcept { return false; // avoid double logging: already logged by write_with_mask() } - mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr): mip_or_mie_csr_t(proc, addr) { } @@ -680,12 +646,10 @@ reg_t mip_csr_t::write_mask() const noexcept { (MIP_SEIP | MIP_SSIP | MIP_STIP | vssip_int); } - mie_csr_t::mie_csr_t(processor_t* const proc, const reg_t addr): mip_or_mie_csr_t(proc, addr) { } - reg_t mie_csr_t::write_mask() const noexcept { const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0; const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0; @@ -695,7 +659,6 @@ reg_t mie_csr_t::write_mask() const noexcept { return all_ints; } - // implement class generic_int_accessor_t generic_int_accessor_t::generic_int_accessor_t(state_t* const state, const reg_t read_mask, @@ -736,7 +699,6 @@ reg_t generic_int_accessor_t::deleg_mask() const { return hideleg_mask & mideleg_mask; } - // implement class mip_proxy_csr_t mip_proxy_csr_t::mip_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr): csr_t(proc, addr), @@ -767,7 +729,6 @@ bool mie_proxy_csr_t::unlogged_write(const reg_t val) noexcept { return false; // accr has already logged } - // implement class mideleg_csr_t mideleg_csr_t::mideleg_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { @@ -795,7 +756,6 @@ bool mideleg_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write(val & delegable_ints); } - // implement class medeleg_csr_t medeleg_csr_t::medeleg_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0), @@ -828,7 +788,6 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } - // implement class masked_csr_t masked_csr_t::masked_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): basic_csr_t(proc, addr, init), @@ -839,20 +798,17 @@ bool masked_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } - // implement class henvcfg_csr_t henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg): masked_csr_t(proc, addr, mask, init), menvcfg(menvcfg) { } - // implement class base_atp_csr_t and family base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } - bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept { const reg_t newval = proc->supports_impl(IMPL_MMU) ? compute_new_satp(val) : 0; if (newval != read()) @@ -926,7 +882,6 @@ bool virtualized_satp_csr_t::unlogged_write(const reg_t val) noexcept { return virtualized_csr_t::unlogged_write(newval); } - // implement class wide_counter_csr_t wide_counter_csr_t::wide_counter_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), @@ -966,7 +921,6 @@ void wide_counter_csr_t::write_upper_half(const reg_t val) noexcept { log_special_write(address + (CSR_MINSTRETH - CSR_MINSTRET), written_value() >> 32); } - counter_top_csr_t::counter_top_csr_t(processor_t* const proc, const reg_t addr, wide_counter_csr_t_p parent): csr_t(proc, addr), parent(parent) { @@ -981,7 +935,6 @@ bool counter_top_csr_t::unlogged_write(const reg_t val) noexcept { return true; } - proxy_csr_t::proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): csr_t(proc, addr), delegate(delegate) { @@ -996,7 +949,6 @@ bool proxy_csr_t::unlogged_write(const reg_t val) noexcept { return false; } - const_csr_t::const_csr_t(processor_t* const proc, const reg_t addr, reg_t val): csr_t(proc, addr), val(val) { @@ -1010,7 +962,6 @@ bool const_csr_t::unlogged_write(const reg_t val) noexcept { return false; } - counter_proxy_csr_t::counter_proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): proxy_csr_t(proc, addr, delegate) { } @@ -1036,7 +987,6 @@ void counter_proxy_csr_t::verify_permissions(insn_t insn, bool write) const { } } - hypervisor_csr_t::hypervisor_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } @@ -1047,7 +997,6 @@ void hypervisor_csr_t::verify_permissions(insn_t insn, bool write) const { throw trap_illegal_instruction(insn.bits()); } - hideleg_csr_t::hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg): masked_csr_t(proc, addr, MIP_VS_MASK, 0), mideleg(mideleg) { @@ -1057,7 +1006,6 @@ reg_t hideleg_csr_t::read() const noexcept { return masked_csr_t::read() & mideleg->read(); }; - hgatp_csr_t::hgatp_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } @@ -1090,7 +1038,6 @@ bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } - tselect_csr_t::tselect_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } @@ -1099,7 +1046,6 @@ bool tselect_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write((val < proc->TM.count()) ? val : read()); } - tdata1_csr_t::tdata1_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr) { } @@ -1112,7 +1058,6 @@ bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept { return proc->TM.tdata1_write(proc, state->tselect->read(), val); } - tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr) { } @@ -1125,7 +1070,6 @@ bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept { return proc->TM.tdata2_write(proc, state->tselect->read(), val); } - debug_mode_csr_t::debug_mode_csr_t(processor_t* const proc, const reg_t addr): basic_csr_t(proc, addr, 0) { } @@ -1146,7 +1090,6 @@ void dpc_csr_t::verify_permissions(insn_t insn, bool write) const { throw trap_illegal_instruction(insn.bits()); } - dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr), prv(0), @@ -1198,7 +1141,6 @@ void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv) noexcept { log_write(); } - float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): masked_csr_t(proc, addr, mask, init) { } @@ -1215,7 +1157,6 @@ bool float_csr_t::unlogged_write(const reg_t val) noexcept { return masked_csr_t::unlogged_write(val); } - composite_csr_t::composite_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb): csr_t(proc, addr), upper_csr(upper_csr), @@ -1239,7 +1180,6 @@ bool composite_csr_t::unlogged_write(const reg_t val) noexcept { return false; // logging is done only by the underlying CSRs } - seed_csr_t::seed_csr_t(processor_t* const proc, const reg_t addr): csr_t(proc, addr) { } @@ -1261,8 +1201,6 @@ bool seed_csr_t::unlogged_write(const reg_t val) noexcept { return true; } - - vector_csr_t::vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): basic_csr_t(proc, addr, init), mask(mask) { @@ -1287,7 +1225,6 @@ bool vector_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write(val & mask); } - vxsat_csr_t::vxsat_csr_t(processor_t* const proc, const reg_t addr): masked_csr_t(proc, addr, /*mask*/ 1, /*init*/ 0) { } diff --git a/riscv/csrs.h b/riscv/csrs.h index f6d2c2c..ab3cdb7 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -57,7 +57,6 @@ class csr_t { typedef std::shared_ptr<csr_t> csr_t_p; - // Basic CSRs, with XLEN bits fully readable and writable. class basic_csr_t: public csr_t { public: @@ -73,7 +72,6 @@ class basic_csr_t: public csr_t { reg_t val; }; - class pmpaddr_csr_t: public csr_t { public: pmpaddr_csr_t(processor_t* const proc, const reg_t addr); @@ -174,7 +172,6 @@ class epc_csr_t: public csr_t { reg_t val; }; - // For mtvec, stvec, and vstvec class tvec_csr_t: public csr_t { public: @@ -187,7 +184,6 @@ class tvec_csr_t: public csr_t { reg_t val; }; - // For mcause, scause, and vscause class cause_csr_t: public basic_csr_t { public: @@ -196,7 +192,6 @@ class cause_csr_t: public basic_csr_t { virtual reg_t read() const noexcept override; }; - // For *status family of CSRs class base_status_csr_t: public csr_t { public: @@ -218,7 +213,6 @@ class base_status_csr_t: public csr_t { typedef std::shared_ptr<base_status_csr_t> base_status_csr_t_p; - // For vsstatus, which is its own separate architectural register // (unlike sstatus) class vsstatus_csr_t final: public base_status_csr_t { @@ -237,7 +231,6 @@ class vsstatus_csr_t final: public base_status_csr_t { typedef std::shared_ptr<vsstatus_csr_t> vsstatus_csr_t_p; - class mstatus_csr_t final: public base_status_csr_t { public: mstatus_csr_t(processor_t* const proc, const reg_t addr); @@ -255,7 +248,6 @@ class mstatus_csr_t final: public base_status_csr_t { typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p; - class mstatush_csr_t: public csr_t { public: mstatush_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus); @@ -267,7 +259,6 @@ class mstatush_csr_t: public csr_t { const reg_t mask; }; - class sstatus_proxy_csr_t final: public base_status_csr_t { public: sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus); @@ -299,7 +290,6 @@ class sstatus_csr_t: public virtualized_csr_t { typedef std::shared_ptr<sstatus_csr_t> sstatus_csr_t_p; - class misa_csr_t final: public basic_csr_t { public: misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa); @@ -320,7 +310,6 @@ class misa_csr_t final: public basic_csr_t { typedef std::shared_ptr<misa_csr_t> misa_csr_t_p; - class mip_or_mie_csr_t: public csr_t { public: mip_or_mie_csr_t(processor_t* const proc, const reg_t addr); @@ -335,7 +324,6 @@ class mip_or_mie_csr_t: public csr_t { virtual reg_t write_mask() const noexcept = 0; }; - // mip is special because some of the bits are driven by hardware pins class mip_csr_t: public mip_or_mie_csr_t { public: @@ -349,7 +337,6 @@ class mip_csr_t: public mip_or_mie_csr_t { typedef std::shared_ptr<mip_csr_t> mip_csr_t_p; - class mie_csr_t: public mip_or_mie_csr_t { public: mie_csr_t(processor_t* const proc, const reg_t addr); @@ -359,7 +346,6 @@ class mie_csr_t: public mip_or_mie_csr_t { typedef std::shared_ptr<mie_csr_t> mie_csr_t_p; - // For sip, hip, hvip, vsip, sie, hie, vsie which are all just (masked // & shifted) views into mip or mie. Each pair will have one of these // objects describing the view, e.g. one for sip+sie, one for hip+hie, @@ -391,7 +377,6 @@ class generic_int_accessor_t { typedef std::shared_ptr<generic_int_accessor_t> generic_int_accessor_t_p; - // For all CSRs that are simply (masked & shifted) views into mip class mip_proxy_csr_t: public csr_t { public: @@ -414,8 +399,6 @@ class mie_proxy_csr_t: public csr_t { generic_int_accessor_t_p accr; }; - - class mideleg_csr_t: public basic_csr_t { public: mideleg_csr_t(processor_t* const proc, const reg_t addr); @@ -425,7 +408,6 @@ class mideleg_csr_t: public basic_csr_t { virtual bool unlogged_write(const reg_t val) noexcept override; }; - class medeleg_csr_t: public basic_csr_t { public: medeleg_csr_t(processor_t* const proc, const reg_t addr); @@ -436,7 +418,6 @@ class medeleg_csr_t: public basic_csr_t { const reg_t hypervisor_exceptions; }; - // For CSRs with certain bits hardwired class masked_csr_t: public basic_csr_t { public: @@ -447,7 +428,6 @@ class masked_csr_t: public basic_csr_t { const reg_t mask; }; - // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 class henvcfg_csr_t final: public masked_csr_t { public: @@ -461,7 +441,6 @@ class henvcfg_csr_t final: public masked_csr_t { csr_t_p menvcfg; }; - // For satp and vsatp // These are three classes in order to handle the [V]TVM bits permission checks class base_atp_csr_t: public basic_csr_t { @@ -492,7 +471,6 @@ class virtualized_satp_csr_t: public virtualized_csr_t { satp_csr_t_p orig_satp; }; - // For minstret and mcycle, which are always 64 bits, but in RV32 are // split into high and low halves. The first class always holds the // full 64-bit value. @@ -512,7 +490,6 @@ class wide_counter_csr_t: public csr_t { typedef std::shared_ptr<wide_counter_csr_t> wide_counter_csr_t_p; - // A simple proxy to read/write the upper half of minstret/mcycle class counter_top_csr_t: public csr_t { public: @@ -526,7 +503,6 @@ class counter_top_csr_t: public csr_t { typedef std::shared_ptr<counter_top_csr_t> counter_top_csr_t_p; - // For a CSR that is an alias of another class proxy_csr_t: public csr_t { public: @@ -538,7 +514,6 @@ class proxy_csr_t: public csr_t { csr_t_p delegate; }; - // For a CSR with a fixed, unchanging value class const_csr_t: public csr_t { public: @@ -550,7 +525,6 @@ class const_csr_t: public csr_t { const reg_t val; }; - // For a CSR that is an unprivileged accessor of a privileged counter class counter_proxy_csr_t: public proxy_csr_t { public: @@ -560,7 +534,6 @@ class counter_proxy_csr_t: public proxy_csr_t { bool myenable(csr_t_p counteren) const noexcept; }; - // For machine-level CSRs that only exist with Hypervisor class hypervisor_csr_t: public basic_csr_t { public: @@ -568,7 +541,6 @@ class hypervisor_csr_t: public basic_csr_t { virtual void verify_permissions(insn_t insn, bool write) const override; }; - class hideleg_csr_t: public masked_csr_t { public: hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg); @@ -577,7 +549,6 @@ class hideleg_csr_t: public masked_csr_t { csr_t_p mideleg; }; - class hgatp_csr_t: public basic_csr_t { public: hgatp_csr_t(processor_t* const proc, const reg_t addr); @@ -586,7 +557,6 @@ class hgatp_csr_t: public basic_csr_t { virtual bool unlogged_write(const reg_t val) noexcept override; }; - class tselect_csr_t: public basic_csr_t { public: tselect_csr_t(processor_t* const proc, const reg_t addr); @@ -594,7 +564,6 @@ class tselect_csr_t: public basic_csr_t { virtual bool unlogged_write(const reg_t val) noexcept override; }; - class tdata1_csr_t: public csr_t { public: tdata1_csr_t(processor_t* const proc, const reg_t addr); @@ -620,7 +589,6 @@ class debug_mode_csr_t: public basic_csr_t { typedef std::shared_ptr<tdata2_csr_t> tdata2_csr_t_p; - class dpc_csr_t: public epc_csr_t { public: dpc_csr_t(processor_t* const proc, const reg_t addr); @@ -648,7 +616,6 @@ class dcsr_csr_t: public csr_t { typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p; - class float_csr_t final: public masked_csr_t { public: float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); @@ -659,7 +626,6 @@ class float_csr_t final: public masked_csr_t { typedef std::shared_ptr<float_csr_t> float_csr_t_p; - // For a CSR like FCSR, that is actually a view into multiple // underlying registers. class composite_csr_t: public csr_t { @@ -676,7 +642,6 @@ class composite_csr_t: public csr_t { const unsigned upper_lsb; }; - class seed_csr_t: public csr_t { public: seed_csr_t(processor_t* const proc, const reg_t addr); @@ -686,7 +651,6 @@ class seed_csr_t: public csr_t { virtual bool unlogged_write(const reg_t val) noexcept override; }; - class vector_csr_t: public basic_csr_t { public: vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init=0); @@ -701,7 +665,6 @@ class vector_csr_t: public basic_csr_t { typedef std::shared_ptr<vector_csr_t> vector_csr_t_p; - // For CSRs shared between Vector and P extensions (vxsat) class vxsat_csr_t: public masked_csr_t { public: diff --git a/riscv/dts.cc b/riscv/dts.cc index 6b47c76..5d37463 100644 --- a/riscv/dts.cc +++ b/riscv/dts.cc @@ -183,7 +183,6 @@ std::string dts_compile(const std::string& dts) return dtb.str(); } - static int fdt_get_node_addr_size(void *fdt, int node, reg_t *addr, unsigned long *size, const char *field) { @@ -245,7 +244,6 @@ static int check_cpu_node(void *fdt, int cpu_offset) return 0; } - int fdt_get_offset(void *fdt, const char *field) { return fdt_path_offset(fdt, field); diff --git a/riscv/entropy_source.h b/riscv/entropy_source.h index 47823ff..184bec7 100644 --- a/riscv/entropy_source.h +++ b/riscv/entropy_source.h @@ -36,7 +36,6 @@ public: // to handle the side-effect of the changing seed value on a read. } - // // The format of seed is described in Section 4.1 of // the scalar cryptography specification. diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 88eb86b..f41be2c 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -372,7 +372,6 @@ void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::stri } } - void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() < 1) diff --git a/riscv/processor.h b/riscv/processor.h index ec1b400..0c6a6b2 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -118,7 +118,6 @@ struct type_sew_t<64> using type=int64_t; }; - // architectural state of a RISC-V hart struct state_t { diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 4d16a58..c9d6161 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -212,5 +212,4 @@ bool module_t::tdata2_write(processor_t * const proc, unsigned index, const reg_ return result; } - }; diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 4df6813..1a2a734 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -201,7 +201,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) if (is_over) \ require(insn.rd() != insn.rs2()); \ - // // vector: loop header and end helper // @@ -291,7 +290,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) require(!(insn.rd() == 0 && P.VU.vflmul > 1)); \ }); - #define INT_ROUNDING(result, xrm, gb) \ do { \ const uint64_t lsb = 1UL << (gb); \ @@ -656,7 +654,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) REDUCTION_ULOOP(e64, BODY) \ } - // genearl VXI signed/unsigned loop #define VI_VV_ULOOP(BODY) \ VI_CHECK_SSS(true) \ @@ -1825,7 +1822,6 @@ reg_t index[P.VU.vlmax]; \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END - #define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(true); \ VI_VFP_LOOP_BASE \ |