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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-19 00:05:02 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-27 19:50:20 -0800 |
| commit | af289070b1ad3d57791e9b2e173a8f525ae6ece2 (patch) | |
| tree | 448dc9976d38320927656141779001a5875ba2e5 /spike_main | |
| parent | 9a672763ed1fed2a68833108205742731c89c7d7 (diff) | |
| download | spike-af289070b1ad3d57791e9b2e173a8f525ae6ece2.zip spike-af289070b1ad3d57791e9b2e173a8f525ae6ece2.tar.gz spike-af289070b1ad3d57791e9b2e173a8f525ae6ece2.tar.bz2 | |
rvv: rename vfncvt suffix and add rod rouding type
1. vfncvt*.v -> vfncvt*.w
2. add vfncvt.rod.f.f.w
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/disasm.cc | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index ddf40a4..3082949 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -1029,15 +1029,23 @@ disassembler_t::disassembler_t(int xlen) add_insn(new disasm_insn_t(#name ".vf", match_##name##_vf, mask_##name##_vf, \ {&vd, &vs2, &frs1, &opt, &vm})); \ - #define DISASM_VFUNARY0_INSN(name, extra) \ - add_insn(new disasm_insn_t(#name "cvt.xu.f.v", match_##name##cvt_xu_f_v, \ - mask_##name##cvt_xu_f_v, {&vd, &vs2, &opt, &vm})); \ - add_insn(new disasm_insn_t(#name "cvt.x.f.v", match_##name##cvt_x_f_v, \ - mask_##name##cvt_x_f_v, {&vd, &vs2, &opt, &vm})); \ - add_insn(new disasm_insn_t(#name "cvt.f.xu.v", match_##name##cvt_f_xu_v, \ - mask_##name##cvt_f_xu_v, {&vd, &vs2, &opt, &vm})); \ - add_insn(new disasm_insn_t(#name "cvt.f.x.v", match_##name##cvt_f_x_v, \ - mask_##name##cvt_f_x_v, {&vd, &vs2, &opt, &vm})); + #define DISASM_VFUNARY0_INSN(name, extra, suf) \ + add_insn(new disasm_insn_t(#name "cvt.xu.f." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ + add_insn(new disasm_insn_t(#name "cvt.x.f." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ + add_insn(new disasm_insn_t(#name "cvt.f.xu." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ + add_insn(new disasm_insn_t(#name "cvt.f.x." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ + if (extra) \ + add_insn(new disasm_insn_t(#name "cvt.f.f." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ //OPFVV/OPFVF //0b01_0000 @@ -1070,14 +1078,12 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV__F_INSN(vfrdiv); //vfunary0 - DISASM_VFUNARY0_INSN(vf, 0); + DISASM_VFUNARY0_INSN(vf, 0, v); - DISASM_VFUNARY0_INSN(vfw, 1); - DISASM_INSN("vfwcvt.f.f.v", vfwcvt_f_f_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_VFUNARY0_INSN(vfw, 1, v); - DISASM_VFUNARY0_INSN(vfn, 1); - DISASM_INSN("vfncvt.f.f.v", vfncvt_f_f_v, 0, {&vd, &vs2, &opt, &vm}); - DISASM_INSN("vfncvt.rod.f.f.v", vfncvt_rod_f_f_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_VFUNARY0_INSN(vfn, 1, w); + DISASM_INSN("vfncvt.rod.f.f.w", vfncvt_rod_f_f_w, 0, {&vd, &vs2, &opt, &vm}); //vfunary1 DISASM_INSN("vfsqrt.v", vfsqrt_v, 0, {&vd, &vs2, &opt, &vm}); |