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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-19 22:04:32 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-27 19:50:20 -0800 |
| commit | 81b1a8334149c71c291155f7fd95f03cba889db8 (patch) | |
| tree | ad2bb888e0657ff5a11ee9525cc41ddc7fb3bd69 /spike_main | |
| parent | af289070b1ad3d57791e9b2e173a8f525ae6ece2 (diff) | |
| download | spike-81b1a8334149c71c291155f7fd95f03cba889db8.zip spike-81b1a8334149c71c291155f7fd95f03cba889db8.tar.gz spike-81b1a8334149c71c291155f7fd95f03cba889db8.tar.bz2 | |
rvv: add load/store whole register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/disasm.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 3082949..9dbd4d0 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -788,6 +788,8 @@ disassembler_t::disassembler_t(int xlen) {"vlseg%dbuff.v",{&vd, &v_address, &opt, &vm}}, }; + + for (size_t idx_insn = 0; idx_insn < sizeof(insn_code) / sizeof(insn_code[0]); ++idx_insn) { const reg_t match_nf = nf << 29; char buf[128]; @@ -800,6 +802,8 @@ disassembler_t::disassembler_t(int xlen) } } + DISASM_INSN("vl1r.v", vl1r_v, 0, {&vd, &v_address}); + DISASM_INSN("vs1r.v", vs1r_v, 0, {&vs3, &v_address}); #define DISASM_OPIV_VXI_INSN(name, sign) \ add_insn(new disasm_insn_t(#name ".vv", match_##name##_vv, mask_##name##_vv, \ |