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authorChih-Min Chao <chihmin.chao@sifive.com>2020-04-13 01:21:38 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-04-14 19:25:45 -0700
commit12255feef8dd5918f02a298123ac30047b3ffc46 (patch)
treebc2c6e2ba587943a9f8d1bd15bb65beef56f53c7 /spike_main
parentd7920cf6c44da6758e88b9635fa0bf94faa648b2 (diff)
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rvv: disasm: leave only SEW-bit segment load/store
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
-rw-r--r--spike_main/disasm.cc66
1 files changed, 0 insertions, 66 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 8b9c985..d8c9eb4 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -697,95 +697,29 @@ disassembler_t::disassembler_t(int xlen)
// handle vector segment load/store
for (size_t nf = 1; nf <= 7; ++nf) {
std::pair<reg_t, reg_t> insn_code[] = {
- {match_vlb_v, mask_vlb_v},
- {match_vlh_v, mask_vlh_v},
- {match_vlw_v, mask_vlw_v},
{match_vle_v, mask_vle_v},
- {match_vlbu_v, mask_vlbu_v},
- {match_vlhu_v, mask_vlhu_v},
- {match_vlwu_v, mask_vlwu_v},
- {match_vsb_v, mask_vsb_v},
- {match_vsh_v, mask_vsh_v},
- {match_vsw_v, mask_vsw_v},
{match_vse_v, mask_vse_v},
- {match_vlsb_v, mask_vlsb_v},
- {match_vlsh_v, mask_vlsh_v},
- {match_vlsw_v, mask_vlsw_v},
{match_vlse_v, mask_vlse_v},
- {match_vlsbu_v, mask_vlsbu_v},
- {match_vlshu_v, mask_vlshu_v},
- {match_vlswu_v, mask_vlswu_v},
- {match_vssb_v, mask_vssb_v},
- {match_vssh_v, mask_vssh_v},
- {match_vssw_v, mask_vssw_v},
{match_vsse_v, mask_vssw_v},
- {match_vlxb_v, mask_vlxb_v},
- {match_vlxh_v, mask_vlxh_v},
- {match_vlxw_v, mask_vlxw_v},
{match_vlxe_v, mask_vlxe_v},
- {match_vlxbu_v, mask_vlxbu_v},
- {match_vlxhu_v, mask_vlxhu_v},
- {match_vlxwu_v, mask_vlxwu_v},
- {match_vsxb_v, mask_vsxb_v},
- {match_vsxh_v, mask_vsxh_v},
- {match_vsxw_v, mask_vsxw_v},
{match_vsxe_v, mask_vsxw_v},
- {match_vlbff_v, mask_vlbff_v},
- {match_vlhff_v, mask_vlhff_v},
- {match_vlwff_v, mask_vlwff_v},
{match_vleff_v, mask_vleff_v},
- {match_vlbuff_v, mask_vlbuff_v},
- {match_vlhuff_v, mask_vlhuff_v},
- {match_vlwuff_v, mask_vlwuff_v},
};
std::pair<const char *, std::vector<const arg_t*>> fmts[] = {
- {"vlseg%db.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dh.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dw.v", {&vd, &v_address, &opt, &vm}},
{"vlseg%de.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dwu.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dhu.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dbu.v", {&vd, &v_address, &opt, &vm}},
- {"vsseg%db.v", {&vs3, &v_address, &opt, &vm}},
- {"vsseg%dh.v", {&vs3, &v_address, &opt, &vm}},
- {"vsseg%dw.v", {&vs3, &v_address, &opt, &vm}},
{"vsseg%de.v", {&vs3, &v_address, &opt, &vm}},
- {"vlsseg%db.v", {&vd, &v_address, &xrs2, &opt, &vm}},
- {"vlsseg%dh.v", {&vd, &v_address, &xrs2, &opt, &vm}},
- {"vlsseg%dw.v", {&vd, &v_address, &xrs2, &opt, &vm}},
{"vlsseg%de.v", {&vd, &v_address, &xrs2, &opt, &vm}},
- {"vlsseg%dbu.v",{&vd, &v_address, &xrs2, &opt, &vm}},
- {"vlsseg%dhu.v",{&vd, &v_address, &xrs2, &opt, &vm}},
- {"vlsseg%dwu.v",{&vd, &v_address, &xrs2, &opt, &vm}},
- {"vssseg%db.v", {&vs3, &v_address, &xrs2, &opt, &vm}},
- {"vssseg%dh.v", {&vs3, &v_address, &xrs2, &opt, &vm}},
- {"vssseg%dw.v", {&vs3, &v_address, &xrs2, &opt, &vm}},
{"vssseg%de.v", {&vs3, &v_address, &xrs2, &opt, &vm}},
- {"vlxseg%db.v", {&vd, &v_address, &vs2, &opt, &vm}},
- {"vlxseg%dh.v", {&vd, &v_address, &vs2, &opt, &vm}},
- {"vlxseg%dw.v", {&vd, &v_address, &vs2, &opt, &vm}},
{"vlxseg%de.v", {&vd, &v_address, &vs2, &opt, &vm}},
- {"vlxseg%dwu.v",{&vd, &v_address, &vs2, &opt, &vm}},
- {"vlxseg%dhu.v",{&vd, &v_address, &vs2, &opt, &vm}},
- {"vlxseg%dbu.v",{&vd, &v_address, &vs2, &opt, &vm}},
- {"vsxseg%db.v", {&vs3, &v_address, &vs2, &opt, &vm}},
- {"vsxseg%dh.v", {&vs3, &v_address, &vs2, &opt, &vm}},
- {"vsxseg%dw.v", {&vs3, &v_address, &vs2, &opt, &vm}},
{"vsxseg%de.v", {&vs3, &v_address, &vs2, &opt, &vm}},
- {"vlseg%dbff.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dhff.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dwff.v", {&vd, &v_address, &opt, &vm}},
{"vlseg%deff.v", {&vd, &v_address, &opt, &vm}},
- {"vlseg%dwuff.v",{&vd, &v_address, &opt, &vm}},
- {"vlseg%dhuff.v",{&vd, &v_address, &opt, &vm}},
- {"vlseg%dbuff.v",{&vd, &v_address, &opt, &vm}},
};