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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 23:15:01 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 23:22:39 -0700 |
| commit | f12bc1f55107db8cc4c59a1695bfa1facb6bb5c4 (patch) | |
| tree | b0814f98f83ba1f1c0a07926c16331adcb7b576c /softfloat/s_add128.c | |
| parent | d3553b5d03fb0a37d657d0534c508354f0378307 (diff) | |
| download | spike-sifive/rvv0.9-phase2.zip spike-sifive/rvv0.9-phase2.tar.gz spike-sifive/rvv0.9-phase2.tar.bz2 | |
rvv: index register doesn't care about NFsifive/rvv0.9-phase2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'softfloat/s_add128.c')
0 files changed, 0 insertions, 0 deletions