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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-22 21:36:05 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:34 -0800 |
commit | f5a68933e509620326d6ff90b449dd074ae915ea (patch) | |
tree | b02ee0b01dcea477c801883901c23c88db6c226b /riscv | |
parent | b15c431738c35417988dd382f3050677efeaa7cc (diff) | |
download | spike-f5a68933e509620326d6ff90b449dd074ae915ea.zip spike-f5a68933e509620326d6ff90b449dd074ae915ea.tar.gz spike-f5a68933e509620326d6ff90b449dd074ae915ea.tar.bz2 |
rvv: add reg checking rule for general fomrat
for most instruction which are in
single, single, single/scalar/immediate format
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 22 | ||||
-rw-r--r-- | riscv/insns/vaadd_vi.h | 1 | ||||
-rw-r--r-- | riscv/insns/vaadd_vv.h | 2 | ||||
-rw-r--r-- | riscv/insns/vaadd_vx.h | 2 | ||||
-rw-r--r-- | riscv/insns/vasub_vv.h | 2 | ||||
-rw-r--r-- | riscv/insns/vasub_vx.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmerge_vim.h | 1 | ||||
-rw-r--r-- | riscv/insns/vmerge_vvm.h | 1 | ||||
-rw-r--r-- | riscv/insns/vmerge_vxm.h | 1 | ||||
-rw-r--r-- | riscv/insns/vmulhsu_vv.h | 1 | ||||
-rw-r--r-- | riscv/insns/vmulhsu_vx.h | 1 | ||||
-rw-r--r-- | riscv/insns/vsadd_vi.h | 1 | ||||
-rw-r--r-- | riscv/insns/vsadd_vv.h | 1 | ||||
-rw-r--r-- | riscv/insns/vsadd_vx.h | 1 | ||||
-rw-r--r-- | riscv/insns/vssub_vv.h | 1 | ||||
-rw-r--r-- | riscv/insns/vssub_vx.h | 1 | ||||
-rw-r--r-- | riscv/insns/vssubu_vv.h | 1 | ||||
-rw-r--r-- | riscv/insns/vssubu_vx.h | 1 |
18 files changed, 38 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d004d11..2fb34ad 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -396,6 +396,17 @@ static inline bool is_overlapped(const int astart, const int asize, } \ } +#define VI_CHECK_SSS(is_vs1) \ + if (P.VU.vlmul > 1) { \ + require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ + require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ + if (is_vs1) { \ + require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \ + } \ + if (insn.v_vm() == 0) \ + require(insn.rd() != 0); \ + } + #define VI_CHECK_SD \ require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul * 2)); @@ -802,6 +813,7 @@ static inline bool is_overlapped(const int astart, const int asize, // genearl VXI signed/unsgied loop #define VI_VV_ULOOP(BODY) \ + VI_CHECK_SSS(true) \ VI_LOOP_BASE \ if (sew == e8){ \ VV_U_PARAMS(e8); \ @@ -819,6 +831,7 @@ static inline bool is_overlapped(const int astart, const int asize, VI_LOOP_END #define VI_VV_LOOP(BODY) \ + VI_CHECK_SSS(true) \ VI_LOOP_BASE \ if (sew == e8){ \ VV_PARAMS(e8); \ @@ -836,6 +849,7 @@ static inline bool is_overlapped(const int astart, const int asize, VI_LOOP_END #define VI_VX_ULOOP(BODY) \ + VI_CHECK_SSS(false) \ VI_LOOP_BASE \ if (sew == e8){ \ VX_U_PARAMS(e8); \ @@ -853,6 +867,7 @@ static inline bool is_overlapped(const int astart, const int asize, VI_LOOP_END #define VI_VX_LOOP(BODY) \ + VI_CHECK_SSS(false) \ VI_LOOP_BASE \ if (sew == e8){ \ VX_PARAMS(e8); \ @@ -870,6 +885,7 @@ static inline bool is_overlapped(const int astart, const int asize, VI_LOOP_END #define VI_VI_ULOOP(BODY) \ + VI_CHECK_SSS(false) \ VI_LOOP_BASE \ if (sew == e8){ \ VI_U_PARAMS(e8); \ @@ -887,6 +903,7 @@ static inline bool is_overlapped(const int astart, const int asize, VI_LOOP_END #define VI_VI_LOOP(BODY) \ + VI_CHECK_SSS(false) \ VI_LOOP_BASE \ if (sew == e8){ \ VI_PARAMS(e8); \ @@ -1293,7 +1310,8 @@ VI_LOOP_END } \ // average loop -#define VI_VVX_LOOP_AVG(opd, op) \ +#define VI_VVX_LOOP_AVG(opd, op, is_vs1) \ +VI_CHECK_SSS(is_vs1); \ VRM xrm = p->VU.get_vround_mode(); \ VI_LOOP_BASE \ switch(sew) { \ @@ -1560,6 +1578,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ set_fp_exceptions; #define VI_VFP_VV_LOOP(BODY) \ + VI_CHECK_SSS(true); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ case e32: {\ @@ -1595,6 +1614,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ VI_VFP_LOOP_REDUCTION_END(e64) #define VI_VFP_VF_LOOP(BODY) \ + VI_CHECK_SSS(false); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ case e32: {\ diff --git a/riscv/insns/vaadd_vi.h b/riscv/insns/vaadd_vi.h index 5f8d5f5..6bd1a60 100644 --- a/riscv/insns/vaadd_vi.h +++ b/riscv/insns/vaadd_vi.h @@ -1,4 +1,5 @@ // vaadd: Averaging adds of integers +VI_CHECK_SSS(false); VRM xrm = P.VU.get_vround_mode(); VI_VI_LOOP ({ diff --git a/riscv/insns/vaadd_vv.h b/riscv/insns/vaadd_vv.h index b479970..0a14467 100644 --- a/riscv/insns/vaadd_vv.h +++ b/riscv/insns/vaadd_vv.h @@ -1,2 +1,2 @@ // vaadd.vv vd, vs2, vs1 -VI_VVX_LOOP_AVG(vs1, +); +VI_VVX_LOOP_AVG(vs1, +, true); diff --git a/riscv/insns/vaadd_vx.h b/riscv/insns/vaadd_vx.h index c811a0a..ae00d8e 100644 --- a/riscv/insns/vaadd_vx.h +++ b/riscv/insns/vaadd_vx.h @@ -1,2 +1,2 @@ // vaadd.vx vd, vs2, rs1 -VI_VVX_LOOP_AVG(rs1, +); +VI_VVX_LOOP_AVG(rs1, +, false); diff --git a/riscv/insns/vasub_vv.h b/riscv/insns/vasub_vv.h index 5a5ccc9..a45c18d 100644 --- a/riscv/insns/vasub_vv.h +++ b/riscv/insns/vasub_vv.h @@ -1,2 +1,2 @@ // vasub.vv vd, vs2, vs1 -VI_VVX_LOOP_AVG(vs1, -); +VI_VVX_LOOP_AVG(vs1, -, true); diff --git a/riscv/insns/vasub_vx.h b/riscv/insns/vasub_vx.h index c3cad4b..4e8dba1 100644 --- a/riscv/insns/vasub_vx.h +++ b/riscv/insns/vasub_vx.h @@ -1,2 +1,2 @@ // vasub.vx vd, vs2, rs1 -VI_VVX_LOOP_AVG(rs1, -); +VI_VVX_LOOP_AVG(rs1, -, false); diff --git a/riscv/insns/vmerge_vim.h b/riscv/insns/vmerge_vim.h index 13354d6..c6c87c7 100644 --- a/riscv/insns/vmerge_vim.h +++ b/riscv/insns/vmerge_vim.h @@ -1,4 +1,5 @@ // vmerge.vim vd, vs2, simm5 +VI_CHECK_SSS(false); VI_VVXI_MERGE_LOOP ({ int midx = (P.VU.vmlen * i) / 64; diff --git a/riscv/insns/vmerge_vvm.h b/riscv/insns/vmerge_vvm.h index 7530b40..97a0182 100644 --- a/riscv/insns/vmerge_vvm.h +++ b/riscv/insns/vmerge_vvm.h @@ -1,4 +1,5 @@ // vmerge.vvm vd, vs2, vs1 +VI_CHECK_SSS(true); VI_VVXI_MERGE_LOOP ({ int midx = (P.VU.vmlen * i) / 64; diff --git a/riscv/insns/vmerge_vxm.h b/riscv/insns/vmerge_vxm.h index b1757fa..de7df91 100644 --- a/riscv/insns/vmerge_vxm.h +++ b/riscv/insns/vmerge_vxm.h @@ -1,4 +1,5 @@ // vmerge.vxm vd, vs2, rs1 +VI_CHECK_SSS(false); VI_VVXI_MERGE_LOOP ({ int midx = (P.VU.vmlen * i) / 64; diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h index 59882da..b918551 100644 --- a/riscv/insns/vmulhsu_vv.h +++ b/riscv/insns/vmulhsu_vv.h @@ -1,4 +1,5 @@ // vmulhsu.vv vd, vs2, vs1 +VI_CHECK_SSS(true); VI_LOOP_BASE switch(sew) { case e8: { diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h index d39615a..cb2db3d 100644 --- a/riscv/insns/vmulhsu_vx.h +++ b/riscv/insns/vmulhsu_vx.h @@ -1,4 +1,5 @@ // vmulhsu.vx vd, vs2, rs1 +VI_CHECK_SSS(false); VI_LOOP_BASE switch(sew) { case e8: { diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index de2cb83..c361f08 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -1,4 +1,5 @@ // vsadd.vi vd, vs2 simm5 +VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; switch(sew) { diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 2152bab..ce0ef40 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -1,4 +1,5 @@ // vsadd.vv vd, vs2, vs1 +VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; switch(sew) { diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h index 781e9e8..691f017 100644 --- a/riscv/insns/vsadd_vx.h +++ b/riscv/insns/vsadd_vx.h @@ -1,4 +1,5 @@ // vsadd.vx vd, vs2, rs1 +VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; switch(sew) { diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h index fd3ee21..18fe4fb 100644 --- a/riscv/insns/vssub_vv.h +++ b/riscv/insns/vssub_vv.h @@ -1,4 +1,5 @@ // vssub.vv vd, vs2, vs1 +VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h index 5c5c781..7a01125 100644 --- a/riscv/insns/vssub_vx.h +++ b/riscv/insns/vssub_vx.h @@ -1,4 +1,5 @@ // vssub.vx vd, vs2, rs1 +VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h index c5c74fe..e58076e 100644 --- a/riscv/insns/vssubu_vv.h +++ b/riscv/insns/vssubu_vv.h @@ -1,4 +1,5 @@ // vssubu.vv vd, vs2, vs1 +VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h index 12cfdbb..556c759 100644 --- a/riscv/insns/vssubu_vx.h +++ b/riscv/insns/vssubu_vx.h @@ -1,4 +1,5 @@ // vssubu.vx vd, vs2, rs1 +VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; |