vext.x.v -> vmv.x.s; unary operation encoding changes

https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac

https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085

4 files changed, 39 insertions, 44 deletions

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 1101f2c..a18a0c9 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -872,7 +872,7 @@
 #define MASK_VFSGNJN_VF  0xfc00707f
 #define MATCH_VFSGNJX_VF 0x28005057
 #define MASK_VFSGNJX_VF  0xfc00707f
-#define MATCH_VFMV_S_F 0x36005057
+#define MATCH_VFMV_S_F 0x42005057
 #define MASK_VFMV_S_F  0xfff0707f
 #define MATCH_VFMERGE_VFM 0x5c005057
 #define MASK_VFMERGE_VFM  0xfe00707f
@@ -956,7 +956,7 @@
 #define MASK_VFSGNJN_VV  0xfc00707f
 #define MATCH_VFSGNJX_VV 0x28001057
 #define MASK_VFSGNJX_VV  0xfc00707f
-#define MATCH_VFMV_F_S 0x32001057
+#define MATCH_VFMV_F_S 0x42001057
 #define MASK_VFMV_F_S  0xfe0ff07f
 #define MATCH_VMFEQ_VV 0x60001057
 #define MASK_VMFEQ_VV  0xfc00707f
@@ -1304,8 +1304,8 @@
 #define MASK_VREDMAXU_VS  0xfc00707f
 #define MATCH_VREDMAX_VS 0x1c002057
 #define MASK_VREDMAX_VS  0xfc00707f
-#define MATCH_VEXT_X_V 0x32002057
-#define MASK_VEXT_X_V  0xfe00707f
+#define MATCH_VMV_X_S 0x42002057
+#define MASK_VMV_X_S  0xfe0ff07f
 #define MATCH_VCOMPRESS_VM 0x5c002057
 #define MASK_VCOMPRESS_VM  0xfc00707f
 #define MATCH_VMANDNOT_MM 0x60002057
@@ -1324,19 +1324,19 @@
 #define MASK_VMNOR_MM  0xfc00707f
 #define MATCH_VMXNOR_MM 0x7c002057
 #define MASK_VMXNOR_MM  0xfc00707f
-#define MATCH_VMSBF_M 0x5800a057
+#define MATCH_VMSBF_M 0x5000a057
 #define MASK_VMSBF_M  0xfc0ff07f
-#define MATCH_VMSOF_M 0x58012057
+#define MATCH_VMSOF_M 0x50012057
 #define MASK_VMSOF_M  0xfc0ff07f
-#define MATCH_VMSIF_M 0x5801a057
+#define MATCH_VMSIF_M 0x5001a057
 #define MASK_VMSIF_M  0xfc0ff07f
-#define MATCH_VIOTA_M 0x58082057
+#define MATCH_VIOTA_M 0x50082057
 #define MASK_VIOTA_M  0xfc0ff07f
-#define MATCH_VID_V 0x5808a057
+#define MATCH_VID_V 0x5008a057
 #define MASK_VID_V  0xfdfff07f
-#define MATCH_VPOPC_M 0x580c2057
+#define MATCH_VPOPC_M 0x40082057
 #define MASK_VPOPC_M  0xfc0ff07f
-#define MATCH_VFIRST_M 0x580ca057
+#define MATCH_VFIRST_M 0x4008a057
 #define MASK_VFIRST_M  0xfc0ff07f
 #define MATCH_VDIVU_VV 0x80002057
 #define MASK_VDIVU_VV  0xfc00707f
@@ -1390,7 +1390,7 @@
 #define MASK_VWMACC_VV  0xfc00707f
 #define MATCH_VWMACCSU_VV 0xf8002057
 #define MASK_VWMACCSU_VV  0xfc00707f
-#define MATCH_VMV_S_X 0x36006057
+#define MATCH_VMV_S_X 0x42006057
 #define MASK_VMV_S_X  0xfff0707f
 #define MATCH_VSLIDE1UP_VX 0x38006057
 #define MASK_VSLIDE1UP_VX  0xfc00707f
@@ -2314,7 +2314,7 @@ DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS)
 DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS)
 DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)
 DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
-DECLARE_INSN(vext_x_v, MATCH_VEXT_X_V, MASK_VEXT_X_V)
+DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
 DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
 DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
 DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
diff --git a/riscv/insns/vext_x_v.h b/riscv/insns/vext_x_v.h
deleted file mode 100644
index 837cc22..0000000
--- a/riscv/insns/vext_x_v.h
+++ /dev/null
@@ -1,30 +0,0 @@
-// vext_x_v: rd = vs2[rs1]
-require(insn.v_vm() == 1);
-uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen());
-reg_t rs1 = RS1;
-VI_LOOP_BASE
-VI_LOOP_END_NO_TAIL_ZERO
-if (!(rs1 >= 0 && rs1 < (P.VU.get_vlen()/sew))) {
-  WRITE_RD(0);
-} else {
-  switch(sew) {
-  case e8:
-    WRITE_RD(P.VU.elt<uint8_t>(rs2_num, rs1));
-    break;
-  case e16:
-    WRITE_RD(P.VU.elt<uint16_t>(rs2_num, rs1));
-    break;
-  case e32:
-    if (P.get_max_xlen() == 32)
-      WRITE_RD(P.VU.elt<int32_t>(rs2_num, rs1));
-    else
-      WRITE_RD(P.VU.elt<uint32_t>(rs2_num, rs1));
-    break;
-  case e64:
-    if (P.get_max_xlen() <= sew)
-      WRITE_RD(P.VU.elt<uint64_t>(rs2_num, rs1) & xmask);
-    else
-      WRITE_RD(P.VU.elt<uint64_t>(rs2_num, rs1));
-    break;
-  }
-}
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h
new file mode 100644
index 0000000..f22c2dd
--- /dev/null
+++ b/riscv/insns/vmv_x_s.h
@@ -0,0 +1,25 @@
+// vext_x_v: rd = vs2[0]
+require(insn.v_vm() == 1);
+uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen());
+VI_LOOP_BASE
+VI_LOOP_END_NO_TAIL_ZERO
+switch(sew) {
+case e8:
+  WRITE_RD(P.VU.elt<uint8_t>(rs2_num, 0));
+  break;
+case e16:
+  WRITE_RD(P.VU.elt<uint16_t>(rs2_num, 0));
+  break;
+case e32:
+  if (P.get_max_xlen() == 32)
+    WRITE_RD(P.VU.elt<int32_t>(rs2_num, 0));
+  else
+    WRITE_RD(P.VU.elt<uint32_t>(rs2_num, 0));
+  break;
+case e64:
+  if (P.get_max_xlen() <= sew)
+    WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0) & xmask);
+  else
+    WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0));
+  break;
+}
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index e672eda..3057c7d 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -312,7 +312,7 @@ riscv_insn_ext_v_alu_int = \
 	vdivu_vx \
 	vdot_vv \
 	vdotu_vv \
-	vext_x_v \
+	vmv_x_s \
 	vid_v \
 	viota_m \
 	vmacc_vv \