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authorAndrew Waterman <andrew@sifive.com>2019-11-24 21:21:31 -0800
committerAndrew Waterman <andrew@sifive.com>2019-11-24 21:21:31 -0800
commitb36b0d66d9357b0c1f52a20233196efcd3ab2404 (patch)
treefebe44db2e94e9a5b53a2e76832ad97f7b372f6b /riscv
parentc3b28ab3c609f1aa2cac5543a10c8a890007f632 (diff)
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Initialize state.misa prior to calls to supports_extension
Partially reverts 0162a6e72421b5cbec1905b4cae7bfab98afe83f Closes #361
Diffstat (limited to 'riscv')
-rw-r--r--riscv/processor.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9b8050c..e8bafcd 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -203,6 +203,8 @@ void processor_t::parse_isa_string(const char* str)
}
}
+ state.misa = max_isa;
+
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);