diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:42:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:53:21 -0700 |
| commit | 88a852836acb4c7166b1aa4102e11354bfd99234 (patch) | |
| tree | 5f592d12aabe3c61d8272a3baac545e4383c33ef /riscv | |
| parent | dd6bc59dcaf5ded29a4463030d35c9b3aa2ad73a (diff) | |
| download | spike-88a852836acb4c7166b1aa4102e11354bfd99234.zip spike-88a852836acb4c7166b1aa4102e11354bfd99234.tar.gz spike-88a852836acb4c7166b1aa4102e11354bfd99234.tar.bz2 | |
Set vtype.vill correctly; also reset it to true
Resolves #313
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 7f61936..b7ef360 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -202,8 +202,9 @@ void vectorUnit_t::reset(){ ELEN = get_elen(); SLEN = get_slen(); // registers are simply concatenated reg_file = malloc(NVPR * (VLEN/8)); - vtype = -1; - set_vl(-1, 0, 0); // vsew8, vlmul1 + + vtype = 0; + set_vl(-1, 0, -1); // default to illegal configuration } reg_t vectorUnit_t::set_vl(uint64_t regId, reg_t reqVL, reg_t newType){ @@ -215,8 +216,12 @@ reg_t vectorUnit_t::set_vl(uint64_t regId, reg_t reqVL, reg_t newType){ vlmax = VLEN/vsew * vlmul; vmlen = vsew / vlmul; reg_mask = (NVPR-1) & ~(vlmul-1); + + vill = vsew > e64 || vediv != 1 || (newType >> 7) != 0; + if (vill) + vlmax = 0; } - vl = reqVL <= vlmax ? (regId == 0)? vlmax: reqVL : vlmax; + vl = reqVL <= vlmax && regId != 0 ? reqVL : vlmax; vstart = 0; setvl_count++; return vl; |