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author | Andrew Waterman <andrew@sifive.com> | 2018-08-23 16:54:36 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-08-23 16:54:36 -0700 |
commit | 747a54b103160bcac7c9dcf721ce3b4703577d73 (patch) | |
tree | 3ae17c87f4b9b0b0c26d82e1976f9965cee698c2 /riscv | |
parent | 60235e3816220eabc6f6e48d103889300d5547df (diff) | |
download | spike-747a54b103160bcac7c9dcf721ce3b4703577d73.zip spike-747a54b103160bcac7c9dcf721ce3b4703577d73.tar.gz spike-747a54b103160bcac7c9dcf721ce3b4703577d73.tar.bz2 |
Add --disable-dtb option to suppress writing the DTB to memory
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/sim.cc | 5 | ||||
-rw-r--r-- | riscv/sim.h | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index b7080f0..44223a7 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -31,7 +31,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, unsigned max_bus_master_bits, bool require_authentication) : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), start_pc(start_pc), current_step(0), current_proc(0), debug(false), - remote_bitbang(NULL), + histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits, require_authentication) { signal(SIGINT, &handle_signal); @@ -202,7 +202,8 @@ char* sim_t::addr_to_mem(reg_t addr) { void sim_t::reset() { - make_dtb(); + if (dtb_enabled) + make_dtb(); } void sim_t::idle() diff --git a/riscv/sim.h b/riscv/sim.h index 97e9ede..b847bdb 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -32,6 +32,9 @@ public: void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); + void set_dtb_enabled(bool value) { + this->dtb_enabled = value; + } void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } @@ -62,6 +65,7 @@ private: bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs + bool dtb_enabled; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines |