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authorChristopher Celio <celio@eecs.berkeley.edu>2014-08-15 15:38:41 -0700
committerChristopher Celio <celio@eecs.berkeley.edu>2014-08-15 15:38:41 -0700
commit616cc32c30ac0684edfd50ed44fc78ed1bc20884 (patch)
tree3ad9cbea79da5a40a5a351e842e1e890a07ad298 /riscv
parente2c0c3021ac2fa7cad5866e0f100c2dbf2372986 (diff)
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Added PC histogram option.
- Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/processor.cc24
-rw-r--r--riscv/processor.h5
-rw-r--r--riscv/riscv.ac5
-rw-r--r--riscv/sim.cc13
-rw-r--r--riscv/sim.h2
5 files changed, 48 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4b282f6..0a2d266 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -35,6 +35,16 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
processor_t::~processor_t()
{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ if (histogram_enabled)
+ {
+ fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
+ for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
+ fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
+ }
+ }
+#endif
+
delete disassembler;
}
@@ -75,6 +85,11 @@ void processor_t::set_debug(bool value)
ext->set_debug(value);
}
+void processor_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+}
+
void processor_t::reset(bool value)
{
if (run == !value)
@@ -118,10 +133,19 @@ static void commit_log(state_t* state, insn_t insn)
#endif
}
+inline void processor_t::update_histogram(size_t pc)
+{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ size_t idx = pc >> 2;
+ pc_histogram[idx]++;
+#endif
+}
+
static inline void execute_insn(processor_t* p, state_t* st, insn_fetch_t fetch)
{
reg_t npc = fetch.func(p, fetch.insn.insn, st->pc);
commit_log(st, fetch.insn.insn);
+ p->update_histogram(st->pc);
st->pc = npc;
}
diff --git a/riscv/processor.h b/riscv/processor.h
index 41268f9..58c31cb 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -6,6 +6,7 @@
#include "config.h"
#include <cstring>
#include <vector>
+#include <map>
class processor_t;
class mmu_t;
@@ -69,6 +70,7 @@ public:
~processor_t();
void set_debug(bool value);
+ void set_histogram(bool value);
void reset(bool value);
void step(size_t n); // run for n cycles
void deliver_ipi(); // register an interprocessor interrupt
@@ -81,6 +83,7 @@ public:
state_t* get_state() { return &state; }
extension_t* get_extension() { return ext; }
void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
+ void update_histogram(size_t pc);
void register_insn(insn_desc_t);
void register_extension(extension_t*);
@@ -94,11 +97,13 @@ private:
uint32_t id;
bool run; // !reset
bool debug;
+ bool histogram_enabled;
bool rv64;
std::vector<insn_desc_t> instructions;
std::vector<insn_desc_t*> opcode_map;
std::vector<insn_desc_t> opcode_store;
+ std::map<size_t,size_t> pc_histogram;
void take_interrupt(); // take a trap if any interrupts are pending
void take_trap(trap_t& t); // take an exception
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index a65039b..4076dc3 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -25,3 +25,8 @@ AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit l
AS_IF([test "x$enable_commitlog" = "xyes"], [
AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation])
])
+
+AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histogram generation]))
+AS_IF([test "x$enable_histogram" = "xyes"], [
+ AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation])
+])
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 59fe593..9490af3 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -40,8 +40,10 @@ sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
debug_mmu = new mmu_t(mem, memsz);
- for (size_t i = 0; i < procs.size(); i++)
+ for (size_t i = 0; i < procs.size(); i++) {
procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+ }
+
}
sim_t::~sim_t()
@@ -124,8 +126,17 @@ void sim_t::set_debug(bool value)
debug = value;
}
+void sim_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i]->set_histogram(histogram_enabled);
+ }
+}
+
void sim_t::set_procs_debug(bool value)
{
for (size_t i=0; i< procs.size(); i++)
procs[i]->set_debug(value);
}
+
diff --git a/riscv/sim.h b/riscv/sim.h
index d437c1a..9e1362e 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -23,6 +23,7 @@ public:
bool running();
void stop();
void set_debug(bool value);
+ void set_histogram(bool value);
void set_procs_debug(bool value);
htif_isasim_t* get_htif() { return htif.get(); }
@@ -48,6 +49,7 @@ private:
size_t current_step;
size_t current_proc;
bool debug;
+ bool histogram_enabled; // provide a histogram of PCs
// presents a prompt for introspection into the simulation
void interactive();