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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-11 15:06:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-11 15:06:20 -0700 |
| commit | 364e9c641257738b3f1ba9f23d9fe0a0ccafce06 (patch) | |
| tree | 24835b5a2dc45c15ebe3dbc8dcd4e4fad4ca7920 /riscv | |
| parent | 44d497f1d8660c404449157a3fe126183cda7966 (diff) | |
| download | spike-364e9c641257738b3f1ba9f23d9fe0a0ccafce06.zip spike-364e9c641257738b3f1ba9f23d9fe0a0ccafce06.tar.gz spike-364e9c641257738b3f1ba9f23d9fe0a0ccafce06.tar.bz2 | |
Fix some 32-bit safety issues
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/dts.cc | 2 | ||||
| -rw-r--r-- | riscv/jtag_dtm.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/riscv/dts.cc b/riscv/dts.cc index cea33ba..f730293 100644 --- a/riscv/dts.cc +++ b/riscv/dts.cc @@ -47,7 +47,7 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, " memory@" << m.first << " {\n" " device_type = \"memory\";\n" " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << - " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" + " 0x" << (m.second->size() >> 16 >> 16) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" " };\n"; } s << " soc {\n" diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc index 3e44c5e..576e495 100644 --- a/riscv/jtag_dtm.cc +++ b/riscv/jtag_dtm.cc @@ -25,8 +25,8 @@ enum { #define DTMCONTROL_DBUSRESET (1<<16) #define DMI_OP 3 -#define DMI_DATA (0xffffffffL<<2) -#define DMI_ADDRESS ((1L<<(abits+34)) - (1L<<34)) +#define DMI_DATA (0xffffffffLL<<2) +#define DMI_ADDRESS ((1LL<<(abits+34)) - (1LL<<34)) #define DMI_OP_STATUS_SUCCESS 0 #define DMI_OP_STATUS_RESERVED 1 |