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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-09 23:43:41 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-19 19:57:00 -0700 |
| commit | e98630e79af962bc203e85f4e446d5a328df12d5 (patch) | |
| tree | 4cc85f9c2e8c589d665b27c48143bfed3be5eaec /riscv | |
| parent | b9f67e66755941b9681a89fa42e9ba80f7fa8351 (diff) | |
| download | spike-e98630e79af962bc203e85f4e446d5a328df12d5.zip spike-e98630e79af962bc203e85f4e446d5a328df12d5.tar.gz spike-e98630e79af962bc203e85f4e446d5a328df12d5.tar.bz2 | |
Rename n_pmp constant to max_pmp
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 4 | ||||
| -rw-r--r-- | riscv/processor.cc | 14 | ||||
| -rw-r--r-- | riscv/processor.h | 6 |
3 files changed, 12 insertions, 12 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 1e8dd8b..6d0b39a 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -204,7 +204,7 @@ reg_t mmu_t::pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode) return true; reg_t base = 0; - for (size_t i = 0; i < proc->state.n_pmp; i++) { + for (size_t i = 0; i < proc->state.max_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; @@ -255,7 +255,7 @@ reg_t mmu_t::pmp_homogeneous(reg_t addr, reg_t len) return true; reg_t base = 0; - for (size_t i = 0; i < proc->state.n_pmp; i++) { + for (size_t i = 0; i < proc->state.max_pmp; i++) { reg_t tor = proc->state.pmpaddr[i] << PMP_SHIFT; uint8_t cfg = proc->state.pmpcfg[i]; diff --git a/riscv/processor.cc b/riscv/processor.cc index d64335f..b3e668a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -657,18 +657,18 @@ void processor_t::set_csr(int which, reg_t val) reg_t delegable_ints = supervisor_ints | coprocessor_ints; reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; - if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) { + if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.max_pmp) { size_t i = which - CSR_PMPADDR0; bool locked = state.pmpcfg[i] & PMP_L; - bool next_locked = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_L); - bool next_tor = i+1 < state.n_pmp && (state.pmpcfg[i+1] & PMP_A) == PMP_TOR; + bool next_locked = i+1 < state.max_pmp && (state.pmpcfg[i+1] & PMP_L); + bool next_tor = i+1 < state.max_pmp && (state.pmpcfg[i+1] & PMP_A) == PMP_TOR; if (!locked && !(next_locked && next_tor)) state.pmpaddr[i] = val & ((reg_t(1) << (MAX_PADDR_BITS - PMP_SHIFT)) - 1); mmu->flush_tlb(); } - if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { + if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.max_pmp / 4) { for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8; i++) { if (!(state.pmpcfg[i] & PMP_L)) { uint8_t cfg = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L); @@ -935,14 +935,14 @@ reg_t processor_t::get_csr(int which) if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31) return 0; - if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.n_pmp) + if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.max_pmp) return state.pmpaddr[which - CSR_PMPADDR0]; - if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.n_pmp / 4) { + if (which >= CSR_PMPCFG0 && which < CSR_PMPCFG0 + state.max_pmp / 4) { require((which & ((xlen / 32) - 1)) == 0); reg_t res = 0; - for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8 && i < state.n_pmp; i++) + for (size_t i0 = (which - CSR_PMPCFG0) * 4, i = i0; i < i0 + xlen / 8 && i < state.max_pmp; i++) res |= reg_t(state.pmpcfg[i]) << (8 * (i - i0)); return res; } diff --git a/riscv/processor.h b/riscv/processor.h index a1acb89..82416f7 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -193,9 +193,9 @@ struct state_t reg_t tdata2[num_triggers]; bool debug_mode; - static const int n_pmp = 16; - uint8_t pmpcfg[n_pmp]; - reg_t pmpaddr[n_pmp]; + static const int max_pmp = 16; + uint8_t pmpcfg[max_pmp]; + reg_t pmpaddr[max_pmp]; uint32_t fflags; uint32_t frm; |