[sim] add vt stuff

47 files changed, 189 insertions, 3 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index bb1f605..c2702a6 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -207,4 +207,49 @@ private:
 #define CRD do_writeback(XPR,(insn.bits >> 5) & 0x1f)
 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 
+// vector stuff
+#define VL vl
+
+#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
+#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
+#define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
+#define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
+#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
+#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
+#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
+#define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
+#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
+              ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
+
+#define UT_LOOP_START for (int i=0;i<VL; i++) {
+#define UT_LOOP_END }
+#define UT_LOOP_RS1 UT_RS1(i)
+#define UT_LOOP_RS2 UT_RS2(i)
+#define UT_LOOP_RD UT_RD(i)
+#define UT_LOOP_RA UT_RA(i)
+#define UT_LOOP_FRS1 UT_FRS1(i)
+#define UT_LOOP_FRS2 UT_FRS2(i)
+#define UT_LOOP_FRS3 UT_FRS3(i)
+#define UT_LOOP_FRD UT_FRD(i)
+#define UT_LOOP_RM UT_RM(i)
+
+#define VEC_LOAD(dst, func, inc) \
+  reg_t addr = RS1; \
+  UT_LOOP_START \
+    UT_LOOP_##dst = mmu.func(addr); \
+    addr += inc; \
+  UT_LOOP_END
+
+#define VEC_STORE(src, func, inc) \
+  reg_t addr = RS1; \
+  UT_LOOP_START \
+    mmu.func(addr, UT_LOOP_##src); \
+    addr += inc; \
+  UT_LOOP_END
+
+enum vt_command_t
+{
+  vt_command_stop,
+};
+
 #endif
diff --git a/riscv/insns/fld_v.h b/riscv/insns/fld_v.h
index e69de29..c2d5072 100644
--- a/riscv/insns/fld_v.h
+++ b/riscv/insns/fld_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int64, 8);
diff --git a/riscv/insns/fldst_v.h b/riscv/insns/fldst_v.h
index e69de29..60f9965 100644
--- a/riscv/insns/fldst_v.h
+++ b/riscv/insns/fldst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int64, RS2);
diff --git a/riscv/insns/flw_v.h b/riscv/insns/flw_v.h
index e69de29..1e54f7e 100644
--- a/riscv/insns/flw_v.h
+++ b/riscv/insns/flw_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int32, 4);
diff --git a/riscv/insns/flwst_v.h b/riscv/insns/flwst_v.h
index e69de29..d11c632 100644
--- a/riscv/insns/flwst_v.h
+++ b/riscv/insns/flwst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_LOAD(FRD, load_int32, RS2);
diff --git a/riscv/insns/fmov_su.h b/riscv/insns/fmov_su.h
index e69de29..65d00ba 100644
--- a/riscv/insns/fmov_su.h
+++ b/riscv/insns/fmov_su.h
@@ -0,0 +1,3 @@
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_FRD(RS2) = FRS1;
diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/fmov_sv.h
index e69de29..b689ed8 100644
--- a/riscv/insns/fmov_sv.h
+++ b/riscv/insns/fmov_sv.h
@@ -0,0 +1,4 @@
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = FRS1;
+UT_LOOP_END
diff --git a/riscv/insns/fmov_us.h b/riscv/insns/fmov_us.h
index e69de29..4052739 100644
--- a/riscv/insns/fmov_us.h
+++ b/riscv/insns/fmov_us.h
@@ -0,0 +1,3 @@
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+FRD = UT_FRS1(RS2);
diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h
index e69de29..28269fd 100644
--- a/riscv/insns/fmov_vv.h
+++ b/riscv/insns/fmov_vv.h
@@ -0,0 +1,4 @@
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = UT_LOOP_FRS1;
+UT_LOOP_END
diff --git a/riscv/insns/fsd_v.h b/riscv/insns/fsd_v.h
index e69de29..28871d5 100644
--- a/riscv/insns/fsd_v.h
+++ b/riscv/insns/fsd_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint64, 8);
diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/fsdst_v.h
index e69de29..9a0b83d 100644
--- a/riscv/insns/fsdst_v.h
+++ b/riscv/insns/fsdst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint64, RS2);
diff --git a/riscv/insns/fsw_v.h b/riscv/insns/fsw_v.h
index e69de29..6cb3580 100644
--- a/riscv/insns/fsw_v.h
+++ b/riscv/insns/fsw_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint32, 4);
diff --git a/riscv/insns/fswst_v.h b/riscv/insns/fswst_v.h
index e69de29..9991e2c 100644
--- a/riscv/insns/fswst_v.h
+++ b/riscv/insns/fswst_v.h
@@ -0,0 +1,2 @@
+require_fp;
+VEC_STORE(FRD, store_uint32, RS2);
diff --git a/riscv/insns/lb_v.h b/riscv/insns/lb_v.h
index e69de29..5246d98 100644
--- a/riscv/insns/lb_v.h
+++ b/riscv/insns/lb_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int8, 1);
diff --git a/riscv/insns/lbst_v.h b/riscv/insns/lbst_v.h
index e69de29..91c8c3a 100644
--- a/riscv/insns/lbst_v.h
+++ b/riscv/insns/lbst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int8, RS2);
diff --git a/riscv/insns/lbu_v.h b/riscv/insns/lbu_v.h
index e69de29..72d9af2 100644
--- a/riscv/insns/lbu_v.h
+++ b/riscv/insns/lbu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint8, 1);
diff --git a/riscv/insns/lbust_v.h b/riscv/insns/lbust_v.h
index e69de29..81ad75f 100644
--- a/riscv/insns/lbust_v.h
+++ b/riscv/insns/lbust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint8, RS2);
diff --git a/riscv/insns/ld_v.h b/riscv/insns/ld_v.h
index e69de29..124f9be 100644
--- a/riscv/insns/ld_v.h
+++ b/riscv/insns/ld_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_LOAD(RD, load_int64, 8);
diff --git a/riscv/insns/ldst_v.h b/riscv/insns/ldst_v.h
index e69de29..84aa0fc 100644
--- a/riscv/insns/ldst_v.h
+++ b/riscv/insns/ldst_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_LOAD(RD, load_int64, RS2);
diff --git a/riscv/insns/lh_v.h b/riscv/insns/lh_v.h
index e69de29..2943110 100644
--- a/riscv/insns/lh_v.h
+++ b/riscv/insns/lh_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int16, 2);
diff --git a/riscv/insns/lhst_v.h b/riscv/insns/lhst_v.h
index e69de29..1bcd364 100644
--- a/riscv/insns/lhst_v.h
+++ b/riscv/insns/lhst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int16, RS2);
diff --git a/riscv/insns/lhu_v.h b/riscv/insns/lhu_v.h
index e69de29..b932aef 100644
--- a/riscv/insns/lhu_v.h
+++ b/riscv/insns/lhu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint16, 2);
diff --git a/riscv/insns/lhust_v.h b/riscv/insns/lhust_v.h
index e69de29..d111428 100644
--- a/riscv/insns/lhust_v.h
+++ b/riscv/insns/lhust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint16, RS2);
diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
index e69de29..980a164 100644
--- a/riscv/insns/lw_v.h
+++ b/riscv/insns/lw_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, 4);
diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
index e69de29..735a620 100644
--- a/riscv/insns/lwst_v.h
+++ b/riscv/insns/lwst_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_int32, RS2);
diff --git a/riscv/insns/lwu_v.h b/riscv/insns/lwu_v.h
index e69de29..b1cdf37 100644
--- a/riscv/insns/lwu_v.h
+++ b/riscv/insns/lwu_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint32, 4);
diff --git a/riscv/insns/lwust_v.h b/riscv/insns/lwust_v.h
index e69de29..7e0c006 100644
--- a/riscv/insns/lwust_v.h
+++ b/riscv/insns/lwust_v.h
@@ -0,0 +1 @@
+VEC_LOAD(RD, load_uint32, RS2);
diff --git a/riscv/insns/mov_su.h b/riscv/insns/mov_su.h
index e69de29..b55ab2f 100644
--- a/riscv/insns/mov_su.h
+++ b/riscv/insns/mov_su.h
@@ -0,0 +1,2 @@
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_RD(RS2) = RS1;
diff --git a/riscv/insns/mov_sv.h b/riscv/insns/mov_sv.h
index e69de29..03bb29d 100644
--- a/riscv/insns/mov_sv.h
+++ b/riscv/insns/mov_sv.h
@@ -0,0 +1,3 @@
+UT_LOOP_START
+  UT_LOOP_RD = RS1;
+UT_LOOP_END
diff --git a/riscv/insns/mov_us.h b/riscv/insns/mov_us.h
index e69de29..05699a8 100644
--- a/riscv/insns/mov_us.h
+++ b/riscv/insns/mov_us.h
@@ -0,0 +1,2 @@
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+RD = UT_RS1(RS2);
diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h
index e69de29..2a1b0b6 100644
--- a/riscv/insns/mov_vv.h
+++ b/riscv/insns/mov_vv.h
@@ -0,0 +1,3 @@
+UT_LOOP_START
+  UT_LOOP_RD = UT_LOOP_RS1;
+UT_LOOP_END
diff --git a/riscv/insns/sb_v.h b/riscv/insns/sb_v.h
index e69de29..81e3513 100644
--- a/riscv/insns/sb_v.h
+++ b/riscv/insns/sb_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint8, 1);
diff --git a/riscv/insns/sbst_v.h b/riscv/insns/sbst_v.h
index e69de29..2d7c59b 100644
--- a/riscv/insns/sbst_v.h
+++ b/riscv/insns/sbst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint8, RS2);
diff --git a/riscv/insns/sd_v.h b/riscv/insns/sd_v.h
index e69de29..330e1b0 100644
--- a/riscv/insns/sd_v.h
+++ b/riscv/insns/sd_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_STORE(RD, store_uint64, 8);
diff --git a/riscv/insns/sdst_v.h b/riscv/insns/sdst_v.h
index e69de29..d3e74d3 100644
--- a/riscv/insns/sdst_v.h
+++ b/riscv/insns/sdst_v.h
@@ -0,0 +1,2 @@
+require_xpr64;
+VEC_STORE(RD, store_uint64, RS2);
diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
index e69de29..5b611db 100644
--- a/riscv/insns/setvl.h
+++ b/riscv/insns/setvl.h
@@ -0,0 +1,2 @@
+setvl(RS1);
+RD = VL;
diff --git a/riscv/insns/sh_v.h b/riscv/insns/sh_v.h
index e69de29..fdfe6fe 100644
--- a/riscv/insns/sh_v.h
+++ b/riscv/insns/sh_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint16, 2);
diff --git a/riscv/insns/shst_v.h b/riscv/insns/shst_v.h
index e69de29..4f4044c 100644
--- a/riscv/insns/shst_v.h
+++ b/riscv/insns/shst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint16, RS2);
diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h
index e69de29..cbf69dc 100644
--- a/riscv/insns/stop.h
+++ b/riscv/insns/stop.h
@@ -0,0 +1,2 @@
+utmode = false;
+throw vt_command_stop;
diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
index e69de29..276da95 100644
--- a/riscv/insns/sw_v.h
+++ b/riscv/insns/sw_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint32, 4);
diff --git a/riscv/insns/swst_v.h b/riscv/insns/swst_v.h
index e69de29..08b198c 100644
--- a/riscv/insns/swst_v.h
+++ b/riscv/insns/swst_v.h
@@ -0,0 +1 @@
+VEC_STORE(RD, store_uint32, RS2);
diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h
index e69de29..70336ac 100644
--- a/riscv/insns/utidx.h
+++ b/riscv/insns/utidx.h
@@ -0,0 +1 @@
+RD = utidx;
diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h
index e69de29..c870f67 100644
--- a/riscv/insns/vcfgivl.h
+++ b/riscv/insns/vcfgivl.h
@@ -0,0 +1,5 @@
+nxpr_use = SIMM & 0x3f;
+nfpr_use = (SIMM >> 6) & 0x3f;
+vcfg();
+setvl(RS1);
+RD = VL;
diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index e69de29..eff542c 100644
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -0,0 +1,7 @@
+for (int i=0; i<VL; i++)
+{
+  uts[i]->pc = RS1+SIMM;
+  uts[i]->utmode = true;
+  while (uts[i]->utmode)
+    uts[i]->step(n, noisy);
+}
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8aa2966..99da902 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -32,6 +32,17 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
 
   memset(counters,0,sizeof(counters));
 
+  // vector stuff
+  utidx = -1;
+  vlmax = 8;
+  vl = 0;
+  nxpr_all = 256;
+  nfpr_all = 256;
+  nxpr_use = 0;
+  nfpr_use = 0;
+  for (int i=0; i<MAX_UTS; i++)
+    uts[i] = NULL;
+
   // a few assumptions about endianness, including freg_t union
   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
   static_assert(sizeof(freg_t) == 8);
@@ -41,9 +52,16 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
 }
 
-void processor_t::init(uint32_t _id)
+void processor_t::init(uint32_t _id, char* _mem, size_t _memsz)
 {
   id = _id;
+
+  for (int i=0; i<MAX_UTS; i++)
+  {
+    uts[i] = new processor_t(sim, _mem, _memsz);
+    uts[i]->set_sr(uts[i]->sr | SR_EF);
+    uts[i]->utidx = i;
+  }
 }
 
 void processor_t::set_sr(uint32_t val)
@@ -67,6 +85,25 @@ void processor_t::set_fsr(uint32_t val)
   fsr = val & ~FSR_ZERO;
 }
 
+void processor_t::vcfg()
+{
+  if (nxpr_use == 0 && nfpr_use == 0)
+    vlmax = 8;
+  else if (nfpr_use == 0)
+    vlmax = (nxpr_all-1) / (nxpr_use-1);
+  else if (nxpr_use == 0)
+    vlmax = (nfpr_all-1) / (nfpr_use-1);
+  else
+    vlmax = std::min((nxpr_all-1) / (nxpr_use-1), (nfpr_all-1) / (nfpr_use-1));
+
+  vlmax = std::min(vlmax, MAX_UTS);
+}
+
+void processor_t::setvl(int vlapp)
+{
+  vl = std::min(vlmax, vlapp);
+}
+
 void processor_t::step(size_t n, bool noisy)
 {
   size_t i = 0;
@@ -101,6 +138,11 @@ void processor_t::step(size_t n, bool noisy)
     i++;
     take_trap(t,noisy);
   }
+  catch(vt_command_t cmd)
+  {
+    if (cmd == vt_command_stop)
+      return;
+  }
 }
 
 void processor_t::take_trap(trap_t t, bool noisy)
diff --git a/riscv/processor.h b/riscv/processor.h
index c1c65ce..34c31ac 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -6,13 +6,15 @@
 #include "trap.h"
 #include "mmu.h"
 
+#define MAX_UTS 32
+
 class sim_t;
 
 class processor_t
 {
 public:
   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
-  void init(uint32_t _id);
+  void init(uint32_t _id, char* _mem, size_t _memsz);
   void step(size_t n, bool noisy);
 
 private:
@@ -55,6 +57,20 @@ private:
   void take_trap(trap_t t, bool noisy);
   void disasm(insn_t insn, reg_t pc);
 
+  // vector stuff
+  void vcfg();
+  void setvl(int vlapp);
+
+  bool utmode;
+  int utidx;
+  int vlmax;
+  int vl;
+  int nxpr_all;
+  int nfpr_all;
+  int nxpr_use;
+  int nfpr_use;
+  processor_t* uts[MAX_UTS];
+
   friend class sim_t;
 };
 
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 56326b5..fbea374 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -15,7 +15,7 @@ sim_t::sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink)
   demand(mem != MAP_FAILED, "couldn't allocate target machine's memory");
 
   for(int i = 0; i < (int)procs.size(); i++)
-    procs[i].init(i);
+    procs[i].init(i, mem, memsz);
 
   applink->init(this);
 }