Use WRITE_RD/WRITE_FRD macros to write registers

141 files changed, 167 insertions, 185 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 3d20b62..bde921f 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -69,22 +69,6 @@ private:
   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
 };
 
-template <class T>
-class write_port_t
-{
-public:
-  write_port_t(T& _t) : t(_t) {}
-  T& operator = (const T& rhs)
-  {
-    return t = rhs;
-  }
-  operator T()
-  {
-    return t;
-  }
-private:
-  T& t;
-};
 template <class T, size_t N, bool zero_reg>
 class regfile_t
 {
@@ -93,11 +77,9 @@ public:
   {
     memset(data, 0, sizeof(data));
   }
-  write_port_t<T> write_port(size_t i)
+  void write(size_t i, T value)
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
-    return write_port_t<T>(data[i]);
+    data[i] = value;
   }
   const T& operator [] (size_t i) const
   {
@@ -113,11 +95,11 @@ private:
 #define MMU (*p->get_mmu())
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
-#define RD p->get_state()->XPR.write_port(insn.rd())
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
-#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())
diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index 34d49ff..d7a5c98 100644
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + RS2);
+WRITE_RD(sext_xprlen(RS1 + RS2));
diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index d6994ba..c861a97 100644
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + insn.i_imm());
+WRITE_RD(sext_xprlen(RS1 + insn.i_imm()));
diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index a0608ed..71ab292 100644
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(insn.i_imm() + RS1);
+WRITE_RD(sext32(insn.i_imm() + RS1));
diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index 4e2ed56..f2d98d9 100644
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 + RS2);
+WRITE_RD(sext32(RS1 + RS2));
diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index bba975c..532902e 100644
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 07c9c9a..8eb9e2b 100644
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index 1bb3402..8a672ba 100644
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 91866dc..32ea7f7 100644
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index dfd2b33..7b97e7b 100644
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index 1f68a8b..a255116 100644
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index 8d50a0a..ef003c6 100644
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index d507e4f..448814b 100644
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);
diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index a20ace8..62915bb 100644
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index d8f95af..28efa15 100644
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 4f83c0f..5543d5e 100644
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index a3a537a..459b201 100644
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);
diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index 87b6f2a..500803f 100644
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index 0733fad..c178f9a 100644
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 3423b91..f03d2aa 100644
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index b888235..148b5bc 100644
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index 25d4fcb..c78e7e3 100644
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index f59a43e..3a87b6e 100644
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);
diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index 88ac1d8..86b4883 100644
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RD = RS1 & RS2;
+WRITE_RD(RS1 & RS2);
diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 713692e..bcc51e4 100644
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RD = insn.i_imm() & RS1;
+WRITE_RD(insn.i_imm() & RS1);
diff --git a/riscv/insns/auipc.h b/riscv/insns/auipc.h
index b58a0c9..4d91bfc 100644
--- a/riscv/insns/auipc.h
+++ b/riscv/insns/auipc.h
@@ -1 +1 @@
-RD = sext_xprlen(insn.u_imm() + (pc >> 12 << 12));
+WRITE_RD(sext_xprlen(insn.u_imm() + (pc >> 12 << 12)));
diff --git a/riscv/insns/clearpcr.h b/riscv/insns/clearpcr.h
index 33e0c31..ac64687 100644
--- a/riscv/insns/clearpcr.h
+++ b/riscv/insns/clearpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm());
+WRITE_RD(p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm()));
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 8412f61..261880f 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = lhs;
+  WRITE_RD(lhs);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 4346349..fd878a2 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,6 +1,6 @@
 reg_t lhs = zext_xprlen(RS1);
 reg_t rhs = zext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 7f6e321..a717658 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index b51d9b7..24f22fd 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -2,6 +2,6 @@ require_xpr64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index dcc6413..e06efb8 100644
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index 952d1a7..c43135d 100644
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index 68c0482..eab849a 100644
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
+WRITE_FRD(i64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index 2032758..bef89eb 100644
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f64(RS1);
+WRITE_FRD(ui64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 6b1a09c..0024330 100644
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_to_f64(FRS1);
+WRITE_FRD(f32_to_f64(FRS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 52abd75..ce56974 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f64((int32_t)RS1);
+WRITE_FRD(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 61a8a78..4c56248 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f64((uint32_t)RS1);
+WRITE_FRD(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index 206ba4f..bf03b71 100644
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i64(FRS1, RM, true);
+WRITE_RD(f64_to_i64(FRS1, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index e05f476..1259234 100644
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i64(FRS1, RM, true);
+WRITE_RD(f32_to_i64(FRS1, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 44c3dd6..d69b36b 100644
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_ui64(FRS1, RM, true);
+WRITE_RD(f64_to_ui64(FRS1, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 13de436..e40605b 100644
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_ui64(FRS1, RM, true);
+WRITE_RD(f32_to_ui64(FRS1, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index e5289c4..28a1d69 100644
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
+WRITE_FRD(f64_to_f32(FRS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index f149229..98570ab 100644
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
+WRITE_FRD(i64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index d9d0946..921bfcf 100644
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f32(RS1);
+WRITE_FRD(ui64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index dedebb5..05445fa 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f32((int32_t)RS1);
+WRITE_FRD(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index abb782c..ca8d2b6 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32((uint32_t)RS1);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index 88dc3d3..a5186b5 100644
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index f14cc19..1d82deb 100644
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 43ad6f6..5cf44d1 100644
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index ff7a11c..5b4c444 100644
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index aa00c98..e215702 100644
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
+WRITE_FRD(f64_div(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index 8c76587..2644d08 100644
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_div(FRS1, FRS2);
+WRITE_FRD(f32_div(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 9db8760..516fb59 100644
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_eq(FRS1, FRS2);
+WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index 658e8f6..b44da24 100644
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_eq(FRS1, FRS2);
+WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 54d4a77..1bc83cf 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));
diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index da76187..72dcc7e 100644
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_le(FRS1, FRS2);
+WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 9c83a17..9c85b4a 100644
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_le(FRS1, FRS2);
+WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 01d135a..335e4a8 100644
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_lt(FRS1, FRS2);
+WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 52eee5d..7a21785 100644
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_lt(FRS1, FRS2);
+WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 1559ecc..a5f7d16 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int32(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));
diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index f67853e..8640e7f 100644
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index 19db642..f8b0a5f 100644
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index cbbb343..a26aeab 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 8df665f..b16134b 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 3d3d454..c095ade 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 994c860..e2fdc5c 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index b1e9340..13e9fcc 100644
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index d3349f5..c6aa418 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index a1462d3..e2ca1c2 100644
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index a954c3d..f564803 100644
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fmv_d_x.h b/riscv/insns/fmv_d_x.h
index 29792ec..35c1977 100644
--- a/riscv/insns/fmv_d_x.h
+++ b/riscv/insns/fmv_d_x.h
@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);
diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index 54546ea..f3eac82 100644
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index a067fd9..5bcf2b5 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-RD = FRS1;
+WRITE_RD(FRS1);
diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index d3d59b2..46a9488 100644
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = sext32(FRS1);
+WRITE_RD(sext32(FRS1));
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 9529aeb..705470b 100644
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 2052b93..2df321b 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index 31a5b39..c38d2bf 100644
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 811a35a..c3fa995 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
 set_fp_exceptions;
diff --git a/riscv/insns/frsr.h b/riscv/insns/frsr.h
index ef121e3..4d80769 100644
--- a/riscv/insns/frsr.h
+++ b/riscv/insns/frsr.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = p->get_fsr();
+WRITE_RD(p->get_fsr());
diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index f66e804..74ef3f6 100644
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));
diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index 35609ac..4f852b4 100644
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index 22de215..e214f1d 100644
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));
diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index dd66d71..b098150 100644
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index 331b6e4..2bcef6f 100644
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & INT64_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));
diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index b455406..69b2d98 100644
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 7647c9c..0ff5daa 100644
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_sqrt(FRS1);
+WRITE_FRD(f64_sqrt(FRS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index 426f241..ea1f31a 100644
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_sqrt(FRS1);
+WRITE_FRD(f32_sqrt(FRS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fssr.h b/riscv/insns/fssr.h
index a9acca6..5695d8c 100644
--- a/riscv/insns/fssr.h
+++ b/riscv/insns/fssr.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = p->set_fsr(RS1);
+WRITE_RD(p->set_fsr(RS1));
diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index fcabe0e..238ee9e 100644
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index 1ff72d2..a30b4f9 100644
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;
diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h
index 9caac55..2694dee 100644
--- a/riscv/insns/jal.h
+++ b/riscv/insns/jal.h
@@ -1,2 +1,2 @@
-RD = npc;
+WRITE_RD(npc);
 set_pc(JUMP_TARGET);
diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index fa6d7f1..3924aa4 100644
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t temp = RS1;
-RD = npc;
+WRITE_RD(npc);
 set_pc((temp + insn.i_imm()) & ~1);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 36acd7b..0f0999c 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = MMU.load_int8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index f1e9472..64d4a68 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RD = MMU.load_uint8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm()));
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index e57daac..d36e172 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int64(RS1 + insn.i_imm()));
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index b158ada..0d458e0 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RD = MMU.load_int16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int16(RS1 + insn.i_imm()));
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 842a752..9d24070 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RD = MMU.load_uint16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm()));
diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 3d2aace..4e8ac18 100644
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,3 +1,3 @@
 require_xpr64;
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int64(RS1);
+WRITE_RD(MMU.load_int64(RS1));
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 7ff48ea..2b95419 100644
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,2 @@
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int32(RS1);
+WRITE_RD(MMU.load_int32(RS1));
diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 8dce543..c7b5264 100644
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RD = insn.u_imm();
+WRITE_RD(insn.u_imm());
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 1b4ea35..4e8ed04 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = MMU.load_int32(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int32(RS1 + insn.i_imm()));
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 6c4ad76..5535baf 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_uint32(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm()));
diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index f711931..a539115 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->get_pcr(insn.rs1());
+WRITE_RD(p->get_pcr(insn.rs1()));
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 2d4121f..ca22db1 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), RS2);
+WRITE_RD(p->set_pcr(insn.rs1(), RS2));
diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 770d733..9725bfd 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 * RS2);
+WRITE_RD(sext_xprlen(RS1 * RS2));
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index f771a62..f63869d 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,7 +2,7 @@ if(xpr64)
 {
   int64_t a = RS1;
   int64_t b = RS2;
-  RD = (int128_t(a) * int128_t(b)) >> 64;
+  WRITE_RD((int128_t(a) * int128_t(b)) >> 64);
 }
 else
-  RD = sext32((sext32(RS1) * sext32(RS2)) >> 32);
+  WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index c832657..d62256e 100644
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,7 +2,7 @@ if(xpr64)
 {
   int64_t a = RS1;
   uint64_t b = RS2;
-  RD = (int128_t(a) * uint128_t(b)) >> 64;
+  WRITE_RD((int128_t(a) * uint128_t(b)) >> 64);
 }
 else
-  RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32);
+  WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32));
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 6334426..2d6f48c 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,4 +1,4 @@
 if(xpr64)
-  RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+  WRITE_RD((uint128_t(RS1) * uint128_t(RS2)) >> 64);
 else
-  RD = sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32);
+  WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32));
diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 7b0a934..9f74fcf 100644
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 * RS2);
+WRITE_RD(sext32(RS1 * RS2));
diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index 07bcac3..3f2fffc 100644
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RD = RS1 | RS2;
+WRITE_RD(RS1 | RS2);
diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 695a56b..6403c39 100644
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RD = insn.i_imm() | RS1;
+WRITE_RD(insn.i_imm() | RS1);
diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h
index 7ebe986..5467f8a 100644
--- a/riscv/insns/rdcycle.h
+++ b/riscv/insns/rdcycle.h
@@ -1 +1 @@
-RD = sext_xprlen(p->get_state()->cycle);
+WRITE_RD(sext_xprlen(p->get_state()->cycle));
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 8094b5b..fa98ac6 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = lhs;
+  WRITE_RD(lhs);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = 0;
+  WRITE_RD(0);
 else
-  RD = sext_xprlen(lhs % rhs);
+  WRITE_RD(sext_xprlen(lhs % rhs));
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 1057789..646bb3a 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,6 +1,6 @@
 reg_t lhs = zext_xprlen(RS1);
 reg_t rhs = zext_xprlen(RS2);
 if(rhs == 0)
-  RD = sext_xprlen(RS1);
+  WRITE_RD(sext_xprlen(RS1));
 else
-  RD = sext_xprlen(lhs % rhs);
+  WRITE_RD(sext_xprlen(lhs % rhs));
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 1ef810c..bec7059 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = sext32(lhs);
+  WRITE_RD(sext32(lhs));
 else
-  RD = sext32(lhs % rhs);
+  WRITE_RD(sext32(lhs % rhs));
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index cc89fa7..b8f4597 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -2,6 +2,6 @@ require_xpr64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
 if(rhs == 0)
-  RD = lhs;
+  WRITE_RD(lhs);
 else
-  RD = sext32(lhs % rhs);
+  WRITE_RD(sext32(lhs % rhs));
diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 9ad962c..3b48244 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -2,7 +2,7 @@ require_xpr64;
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint64(RS1, RS2);
-  RD = 0;
+  WRITE_RD(0);
 }
 else
-  RD = 1;
+  WRITE_RD(1);
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 3ad79ac..729973d 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,7 +1,7 @@
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint32(RS1, RS2);
-  RD = 0;
+  WRITE_RD(0);
 }
 else
-  RD = 1;
+  WRITE_RD(1);
diff --git a/riscv/insns/setpcr.h b/riscv/insns/setpcr.h
index 2876670..f001827 100644
--- a/riscv/insns/setpcr.h
+++ b/riscv/insns/setpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm());
+WRITE_RD(p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm()));
diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 86eb966..48c0acf 100644
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 << (RS2 & (xprlen-1)));
+WRITE_RD(sext_xprlen(RS1 << (RS2 & (xprlen-1))));
diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 151d970..ff9c8c3 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = RS1 << SHAMT;
+  WRITE_RD(RS1 << SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32(RS1 << SHAMT);
+  WRITE_RD(sext32(RS1 << SHAMT));
 }
diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 8ef4ae7..fdb51be 100644
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << SHAMT);
+WRITE_RD(sext32(RS1 << SHAMT));
diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index f3356d8..25e717a 100644
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << (RS2 & 0x1F));
+WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));
diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 5c50534..dd6e58e 100644
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
+WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 51873f3..18d32da 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm()));
+WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm())));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 924fc92..ff4eae1 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(insn.i_imm());
+WRITE_RD(cmp_trunc(RS1) < cmp_trunc(insn.i_imm()));
diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 2c5bdc3..3a353fd 100644
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(RS2);
+WRITE_RD(cmp_trunc(RS1) < cmp_trunc(RS2));
diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 7102da0..45c9657 100644
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1)));
+WRITE_RD(sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1))));
diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 7360d5f..7fdbdf3 100644
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = sreg_t(RS1) >> SHAMT;
+  WRITE_RD(sreg_t(RS1) >> SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32(int32_t(RS1) >> SHAMT);
+  WRITE_RD(sext32(int32_t(RS1) >> SHAMT));
 }
diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index f43b3fb..242c97e 100644
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> SHAMT);
+WRITE_RD(sext32(int32_t(RS1) >> SHAMT));
diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index d178374..29640bf 100644
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> (RS2 & 0x1F));
+WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F)));
diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 8230d27..9b1eb21 100644
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,4 +1,4 @@
 if(xpr64)
-  RD = RS1 >> (RS2 & 0x3F);
+  WRITE_RD(RS1 >> (RS2 & 0x3F));
 else
-  RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+  WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F)));
diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index f5b8c02..fee136c 100644
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,8 +1,8 @@
 if(xpr64)
-  RD = RS1 >> SHAMT;
+  WRITE_RD(RS1 >> SHAMT);
 else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction();
-  RD = sext32((uint32_t)RS1 >> SHAMT);
+  WRITE_RD(sext32((uint32_t)RS1 >> SHAMT));
 }
diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 2ee1be0..0b6f9b8 100644
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> SHAMT);
+WRITE_RD(sext32((uint32_t)RS1 >> SHAMT));
diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index b206f7c..21ca502 100644
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F)));
diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 2b1e057..95fb83e 100644
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 - RS2);
+WRITE_RD(sext_xprlen(RS1 - RS2));
diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 28db334..dce982f 100644
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,3 +1,3 @@
 require_xpr64;
-RD = sext32(RS1 - RS2);
+WRITE_RD(sext32(RS1 - RS2));
 
diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 49b1783..771efa7 100644
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RD = RS1 ^ RS2;
+WRITE_RD(RS1 ^ RS2);
diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 4eba233..33ce630 100644
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RD = insn.i_imm() ^ RS1;
+WRITE_RD(insn.i_imm() ^ RS1);
diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index 3e8596f..a4766d4 100644
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -18,7 +18,7 @@ union rocc_insn_union_t
     reg_t xs2 = u.r.xs1 ? RS2 : -1; \
     reg_t xd = rocc->custom##n(u.r, xs1, xs2); \
     if (u.r.xd) \
-      RD = xd; \
+      WRITE_RD(xd); \
     return pc+4; \
   } \
   \