fixed: xext, vmulh[u]_v[vx], vsne_vi

8 files changed, 26 insertions, 20 deletions

diff --git a/riscv/insns/vext_x_v.h b/riscv/insns/vext_x_v.h
index eba3b05..877cd14 100644
--- a/riscv/insns/vext_x_v.h
+++ b/riscv/insns/vext_x_v.h
@@ -1,3 +1,5 @@
 // vext_x_v: rd = vs2[rs1]
-reg_t vs2_num = insn.rs2(); 
-WRITE_RD(STATE.VU.elt<int32_t>(vs2_num, RS1));
+VI_XV_LOOP({
+	WRITE_RD(vs2);
+	break;
+})
diff --git a/riscv/insns/vmul_vv.h b/riscv/insns/vmul_vv.h
index eda3c5e..2d4bc4e 100644
--- a/riscv/insns/vmul_vv.h
+++ b/riscv/insns/vmul_vv.h
@@ -1,9 +1,9 @@
 // vmul
 reg_t vsew = STATE.VU.vsew;
-uint64_t lo_mask = 1 - ((1 << vsew) - 1);
+uint64_t lo_mask = ((uint64_t)1 << vsew) - 1;
 
 VI_VV_LOOP
 ({
-    uint64_t result = vs1 * vs2;
-	vd = vsext(result & lo_mask, sew);
+    int64_t result = vs1 * vs2;
+	vd = result & lo_mask;
 })
diff --git a/riscv/insns/vmul_vx.h b/riscv/insns/vmul_vx.h
index b45098e..0a77af0 100644
--- a/riscv/insns/vmul_vx.h
+++ b/riscv/insns/vmul_vx.h
@@ -1,9 +1,9 @@
 // vmul
 reg_t vsew = STATE.VU.vsew;
-uint64_t lo_mask = 1 - ((1 << vsew) - 1);
+uint64_t lo_mask = ((uint64_t)1 << vsew) - 1;
 
 VI_VX_LOOP
 ({
-    uint64_t result = rs1 * vs2;
-	vd = vsext(result & lo_mask, sew);
+    int64_t result = rs1 * vs2;
+	vd = result & lo_mask;
 })
diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h
index f7eb041..4f3c01c 100644
--- a/riscv/insns/vmulh_vv.h
+++ b/riscv/insns/vmulh_vv.h
@@ -1,9 +1,9 @@
 // vmulh
 reg_t vsew = STATE.VU.vsew;
-uint64_t lo_mask = 1 - ((1 << vsew) - 1);
+uint64_t lo_mask = ((uint64_t)1 << vsew) - 1;
 
 VI_VV_LOOP
 ({
-    uint64_t result = vs1 * vs2;
-	vd = vsext((result >> sew) & lo_mask, sew);
+    int64_t result = (int64_t)vs1 * (int64_t)vs2;
+	vd = (result >> sew) & lo_mask;
 })
diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h
index a7bf7aa..1898950 100644
--- a/riscv/insns/vmulh_vx.h
+++ b/riscv/insns/vmulh_vx.h
@@ -1,5 +1,9 @@
 // vmulh
+reg_t vsew = STATE.VU.vsew;
+uint64_t lo_mask = ((uint64_t)1 << vsew) - 1;
+
 VI_VX_LOOP
 ({
-	vd = vsext((rs1 * vs2) >> (sew/2), sew);
+    int64_t result = (int64_t)rs1 * (int64_t)vs2;
+	vd = (result >> sew) & lo_mask;
 })
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
index 4aff1a2..46e5d46 100644
--- a/riscv/insns/vmulhu_vv.h
+++ b/riscv/insns/vmulhu_vv.h
@@ -1,11 +1,10 @@
 // vmulhu: Unsigned multiply, returning high bits of product
 require(STATE.VU.ELEN <= 32);
 reg_t vsew = STATE.VU.vsew;
-uint64_t sew_result_bits = vsew * 2;
-uint64_t upper_mask = 1 - ((1 << vsew) - 1);
+uint64_t lo_mask = (((uint64_t)1 << vsew) - 1);
 
 VI_VV_LOOP
 ({
-    uint64_t result = vs1 * vs2;
-    vd = (result>>(sew_result_bits - sew)) & upper_mask;
+    uint64_t result = (uint64_t)vs1 * (uint64_t)vs2;
+    vd = (result >> sew) & lo_mask;
 })
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index 1b20ac8..ffce3b5 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -1,4 +1,5 @@
 // vmv_s_x: vd[0] = rs1
-
-reg_t rd_num = insn.rd(); 
-STATE.VU.elt<int32_t>(rd_num, 0) = RS1;
+VI_XV_LOOP({
+	vd = RS1;
+	break;
+})
diff --git a/riscv/insns/vsne_vi.h b/riscv/insns/vsne_vi.h
index eea505b..8834778 100644
--- a/riscv/insns/vsne_vi.h
+++ b/riscv/insns/vsne_vi.h
@@ -1,5 +1,5 @@
 // vsne
 VI_VI_LOOP
 ({
-    vd = !(simm5 == sreg_t(vs2));
+    vd = (simm5 != vs2) ? 1 : 0;
 })