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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-18 21:19:28 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-18 21:19:28 -0700 |
commit | 62814109390b358e5190bd4789dc1a0cfc3e7253 (patch) | |
tree | b0d8b8381e7047d8de116782e6b6cb22da7a2eec /riscv | |
parent | 74b220698fb1a46e0279bba244de8b8ac3348403 (diff) | |
download | spike-62814109390b358e5190bd4789dc1a0cfc3e7253.zip spike-62814109390b358e5190bd4789dc1a0cfc3e7253.tar.gz spike-62814109390b358e5190bd4789dc1a0cfc3e7253.tar.bz2 |
rvv: fix unit/stride emul calculation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f547ec8..5731ae1 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -474,7 +474,7 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_CHECK_STORE \ require_vector; \ - reg_t emul = (eew / P.VU.vsew * P.VU.vlmul) + 0.75; \ + reg_t emul = (eew / P.VU.vsew * P.VU.vlmul) + 0.875; \ require(emul >= 1 && emul <= 8); \ require((insn.rd() & (emul - 1)) == 0); \ require((nf * emul) <= (NVPR / 4) && \ @@ -1610,7 +1610,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ const reg_t vl = P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ - const reg_t eew = sizeof(st_width##_t) * 8; \ + const float eew = sizeof(st_width##_t) * 8; \ VI_CHECK_STORE; \ for (reg_t i = 0; i < vl; ++i) { \ VI_STRIP(i) \ @@ -1666,7 +1666,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ const reg_t vl = p->VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t rd_num = insn.rd(); \ - const reg_t eew = sizeof(ld_type##_t) * 8; \ + const float eew = sizeof(ld_type##_t) * 8; \ VI_CHECK_LOAD; \ bool early_stop = false; \ for (reg_t i = p->VU.vstart; i < vl; ++i) { \ |