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| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | 2020-02-28 13:50:38 +0000 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 22:48:23 -0800 |
| commit | 2863b3132c874a37c5b9ee5bd0989772623ce97a (patch) | |
| tree | 877ec46aae3f91bf282fc032f8cccd357933ead4 /riscv | |
| parent | d9ec9c37b1542cc50b3717f140351d2f403fc921 (diff) | |
| download | spike-2863b3132c874a37c5b9ee5bd0989772623ce97a.zip spike-2863b3132c874a37c5b9ee5bd0989772623ce97a.tar.gz spike-2863b3132c874a37c5b9ee5bd0989772623ce97a.tar.bz2 | |
Add do-nothing support for mcountinhibit CSR
This CSR appeared in version 1.11 of the ISA and is described in the
Volume II: Privileged Architecture manual. It's an optional register
and should read as zero if not implemented, which is what this patch
does.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/encoding.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 26142db..a1d6c7c 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1617,6 +1617,7 @@ #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +#define CSR_MCOUNTINHIBIT 0x320 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -2538,6 +2539,7 @@ DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) diff --git a/riscv/processor.cc b/riscv/processor.cc index 571bbda..94c8c76 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -900,6 +900,7 @@ reg_t processor_t::get_csr(int which) break; case CSR_SCOUNTEREN: return state.scounteren; case CSR_MCOUNTEREN: return state.mcounteren; + case CSR_MCOUNTINHIBIT: return 0; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | (supports_extension('V') ? SSTATUS_VS : 0) |