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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-10 00:03:08 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-19 19:57:04 -0700 |
| commit | 1028871cf96008744744aa39d88c496a71792125 (patch) | |
| tree | fd41786e407ddb63e081be44860148bc61543b45 /riscv | |
| parent | 1e0fab92b1d6f350fc1f4f0093f5976588bd3afa (diff) | |
| download | spike-1028871cf96008744744aa39d88c496a71792125.zip spike-1028871cf96008744744aa39d88c496a71792125.tar.gz spike-1028871cf96008744744aa39d88c496a71792125.tar.bz2 | |
Disable PMP checks when configuration includes zero PMP registers
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 6d0b39a..3b0eb0d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -200,7 +200,7 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ reg_t mmu_t::pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode) { - if (!proc) + if (!proc || proc->n_pmp == 0) return true; reg_t base = 0; |