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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-06 14:53:32 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-06 19:30:40 -0700 |
| commit | fd50768df9ec4d9f80c6a37d89734d9e27443f6b (patch) | |
| tree | 89c11f72f754d038dee12b0129237dd2c11d1c3a /riscv | |
| parent | 197f3e2640a182c7734d781bf61f570457cce5b8 (diff) | |
| download | spike-fd50768df9ec4d9f80c6a37d89734d9e27443f6b.zip spike-fd50768df9ec4d9f80c6a37d89734d9e27443f6b.tar.gz spike-fd50768df9ec4d9f80c6a37d89734d9e27443f6b.tar.bz2 | |
Fix endianness bug in fetch triggers
Instruction fetch is always little-endian.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index f87e879..b8690ec 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -93,8 +93,7 @@ tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr) result = tlb_data[vpn % TLB_ENTRIES]; } - target_endian<uint16_t>* ptr = (target_endian<uint16_t>*)(result.host_offset + vaddr); - check_triggers(triggers::OPERATION_EXECUTE, vaddr, true, from_target(*ptr)); + check_triggers(triggers::OPERATION_EXECUTE, vaddr, true, from_le(*(const uint16_t*)(result.host_offset + vaddr))); return result; } |