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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 00:48:10 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:36:14 -0700 |
| commit | fb84a685a89603eb91bd36261addc0fd13d2b576 (patch) | |
| tree | 8bdfc2b3d7a4dcc69bbf746ed230c7f31e7b7c68 /riscv | |
| parent | d4f881d0ecce46c6f011603aeb74ad3a72b28fbf (diff) | |
| download | spike-fb84a685a89603eb91bd36261addc0fd13d2b576.zip spike-fb84a685a89603eb91bd36261addc0fd13d2b576.tar.gz spike-fb84a685a89603eb91bd36261addc0fd13d2b576.tar.bz2 | |
rvv: extenc VU structure to support 0.9 new fields
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/execute.cc | 6 | ||||
| -rw-r--r-- | riscv/processor.cc | 23 | ||||
| -rw-r--r-- | riscv/processor.h | 7 |
3 files changed, 28 insertions, 8 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 6f484c5..b18a55d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -107,7 +107,11 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } if (!show_vec && (is_vreg || is_vec)) { - fprintf(log_file, " e%ld m%ld l%ld", p->VU.vsew, p->VU.vlmul, p->VU.vl); + fprintf(log_file, " e%ld %s%ld l%ld", + p->VU.vsew, + p->VU.vflmul < 0 ? "mf" : "m", + p->VU.vflmul < 0 ? (1 / p->VU.vflmul) : p->VU.vflmul, + p->VU.vl); show_vec = true; } diff --git a/riscv/processor.cc b/riscv/processor.cc index 12119d4..123a8cc 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -355,16 +355,27 @@ void processor_t::vectorUnit_t::reset(){ } reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType){ + int new_vlmul = 0; if (vtype != newType){ vtype = newType; vsew = 1 << (BITS(newType, 4, 2) + 3); - vlmul = 1 << BITS(newType, 1, 0); - vediv = 1 << BITS(newType, 6, 5); - vlmax = VLEN/vsew * vlmul; - vmlen = vsew / vlmul; - reg_mask = (NVPR-1) & ~(vlmul-1); + new_vlmul = (BITS(newType, 5, 5) << 2) | BITS(newType, 1, 0); + new_vlmul = (int8_t)(new_vlmul << 5) >> 5; + vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul); + vlmul = vflmul < 1 ? 1 : vflmul; + vlmax = (VLEN/vsew) * vflmul; + vemul = vflmul; + veew = vsew; + vta = BITS(newType, 6, 6); + vma = BITS(newType, 7, 7); + vediv = 1 << BITS(newType, 9, 8); + + vill = !(vflmul >= 0.125 && vflmul <= 8) + || vsew > ELEN + || vflmul < ((float)vsew / ELEN) + || vediv != 1 + || (newType >> 8) != 0; - vill = vsew > ELEN || vediv != 1 || (newType >> 7) != 0; if (vill) { vlmax = 0; vtype = UINT64_MAX << (p->get_xlen() - 1); diff --git a/riscv/processor.h b/riscv/processor.h index c251340..7d2e372 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -453,9 +453,14 @@ public: void *reg_file; char reg_referenced[NVPR]; int setvl_count; - reg_t reg_mask, vlmax, vmlen; + reg_t vlmax; reg_t vstart, vxrm, vxsat, vl, vtype, vlenb; + reg_t vma, vta; reg_t vediv, vsew, vlmul; + reg_t veew; + float vemul; + float vflmul; + reg_t vmel; reg_t ELEN, VLEN, SLEN; bool vill; |