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author | Tim Newsome <tim@sifive.com> | 2017-02-12 10:20:37 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2017-02-12 10:20:37 -0800 |
commit | f7f110504072dc601a24a4391cbf3b0091a47a12 (patch) | |
tree | 4f1a23d0aa5d1cf2d83192a9df3336404f28f489 /riscv | |
parent | b4de20a92e48e9e08872323675bdd4bbf07b37d6 (diff) | |
download | spike-f7f110504072dc601a24a4391cbf3b0091a47a12.zip spike-f7f110504072dc601a24a4391cbf3b0091a47a12.tar.gz spike-f7f110504072dc601a24a4391cbf3b0091a47a12.tar.bz2 |
Fix stack overflow and support --rbb-port=0
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/debug_defines.h | 98 | ||||
-rw-r--r-- | riscv/debug_module.cc | 18 | ||||
-rw-r--r-- | riscv/debug_module.h | 1 | ||||
-rw-r--r-- | riscv/jtag_dtm.cc | 1 | ||||
-rw-r--r-- | riscv/remote_bitbang.cc | 15 |
5 files changed, 88 insertions, 45 deletions
diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h index 7dc46ea..f9fdaa0 100644 --- a/riscv/debug_defines.h +++ b/riscv/debug_defines.h @@ -1,10 +1,4 @@ #define AC_ACCESS_REGISTER None -#define AC_ACCESS_REGISTER_PREHALT_OFFSET 23 -#define AC_ACCESS_REGISTER_PREHALT_LENGTH 1 -#define AC_ACCESS_REGISTER_PREHALT (0x1 << AC_ACCESS_REGISTER_PREHALT_OFFSET) -#define AC_ACCESS_REGISTER_POSTRESUME_OFFSET 22 -#define AC_ACCESS_REGISTER_POSTRESUME_LENGTH 1 -#define AC_ACCESS_REGISTER_POSTRESUME (0x1 << AC_ACCESS_REGISTER_POSTRESUME_OFFSET) #define AC_ACCESS_REGISTER_SIZE_OFFSET 19 #define AC_ACCESS_REGISTER_SIZE_LENGTH 3 #define AC_ACCESS_REGISTER_SIZE (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET) @@ -20,6 +14,10 @@ #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16 #define AC_ACCESS_REGISTER_REGNO (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET) +#define AC_QUICK_ACCESS None +#define AC_QUICK_ACCESS_1_OFFSET 24 +#define AC_QUICK_ACCESS_1_LENGTH 8 +#define AC_QUICK_ACCESS_1 (0xff << AC_QUICK_ACCESS_1_OFFSET) #define CSR_DCSR 0x7b0 #define CSR_DCSR_XDEBUGVER_OFFSET 30 #define CSR_DCSR_XDEBUGVER_LENGTH 2 @@ -89,6 +87,16 @@ #define DMI_DMCONTROL_VERSION_OFFSET 0 #define DMI_DMCONTROL_VERSION_LENGTH 4 #define DMI_DMCONTROL_VERSION (0xf << DMI_DMCONTROL_VERSION_OFFSET) +#define DMI_HARTINFO 0x01 +#define DMI_HARTINFO_DATAACCESS_OFFSET 16 +#define DMI_HARTINFO_DATAACCESS_LENGTH 1 +#define DMI_HARTINFO_DATAACCESS (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET) +#define DMI_HARTINFO_DATASIZE_OFFSET 12 +#define DMI_HARTINFO_DATASIZE_LENGTH 4 +#define DMI_HARTINFO_DATASIZE (0xf << DMI_HARTINFO_DATASIZE_OFFSET) +#define DMI_HARTINFO_DATAADDR_OFFSET 0 +#define DMI_HARTINFO_DATAADDR_LENGTH 12 +#define DMI_HARTINFO_DATAADDR (0xfff << DMI_HARTINFO_DATAADDR_OFFSET) #define DMI_HALTSUM 0x02 #define DMI_HALTSUM_HALT1023_992_OFFSET 31 #define DMI_HALTSUM_HALT1023_992_LENGTH 1 @@ -251,7 +259,15 @@ #define DMI_SBDATA3_DATA_OFFSET 0 #define DMI_SBDATA3_DATA_LENGTH 32 #define DMI_SBDATA3_DATA (0xffffffff << DMI_SBDATA3_DATA_OFFSET) -#define DMI_ABSTRACTCS 0x0b +#define DMI_AUTHDATA0 0x0b +#define DMI_AUTHDATA0_DATA_OFFSET 0 +#define DMI_AUTHDATA0_DATA_LENGTH 32 +#define DMI_AUTHDATA0_DATA (0xffffffff << DMI_AUTHDATA0_DATA_OFFSET) +#define DMI_AUTHDATA1 0x0c +#define DMI_AUTHDATA1_DATA_OFFSET 0 +#define DMI_AUTHDATA1_DATA_LENGTH 32 +#define DMI_AUTHDATA1_DATA (0xffffffff << DMI_AUTHDATA1_DATA_OFFSET) +#define DMI_ABSTRACTCS 0x0e #define DMI_ABSTRACTCS_AUTOEXEC7_OFFSET 15 #define DMI_ABSTRACTCS_AUTOEXEC7_LENGTH 1 #define DMI_ABSTRACTCS_AUTOEXEC7 (0x1 << DMI_ABSTRACTCS_AUTOEXEC7_OFFSET) @@ -285,49 +301,30 @@ #define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4 #define DMI_ABSTRACTCS_DATACOUNT (0xf << DMI_ABSTRACTCS_DATACOUNT_OFFSET) -#define DMI_COMMAND 0x0c +#define DMI_COMMAND 0x0f #define DMI_COMMAND_COMMAND_OFFSET 0 #define DMI_COMMAND_COMMAND_LENGTH 32 #define DMI_COMMAND_COMMAND (0xffffffff << DMI_COMMAND_COMMAND_OFFSET) -#define DMI_DATA0 0x0d +#define DMI_DATA0 0x10 #define DMI_DATA0_DATA_OFFSET 0 #define DMI_DATA0_DATA_LENGTH 32 #define DMI_DATA0_DATA (0xffffffff << DMI_DATA0_DATA_OFFSET) -#define DMI_DATA1 0x0e -#define DMI_DATA2 0x0f -#define DMI_DATA3 0x10 -#define DMI_DATA4 0x11 -#define DMI_DATA5 0x12 -#define DMI_DATA6 0x13 -#define DMI_DATA7 0x14 -#define DMI_ACCESSCS 0x15 -#define DMI_ACCESSCS_PROGSIZE_OFFSET 0 -#define DMI_ACCESSCS_PROGSIZE_LENGTH 4 -#define DMI_ACCESSCS_PROGSIZE (0xf << DMI_ACCESSCS_PROGSIZE_OFFSET) -#define DMI_IBUF0 0x18 -#define DMI_IBUF0_DATA_OFFSET 0 -#define DMI_IBUF0_DATA_LENGTH 32 -#define DMI_IBUF0_DATA (0xffffffff << DMI_IBUF0_DATA_OFFSET) -#define DMI_IBUF1 0x19 -#define DMI_IBUF2 0x1a -#define DMI_IBUF3 0x1b -#define DMI_IBUF4 0x1c -#define DMI_IBUF5 0x1d -#define DMI_IBUF6 0x1e -#define DMI_IBUF7 0x1f -#define DMI_AUTHDATA0 0x20 -#define DMI_AUTHDATA0_DATA_OFFSET 0 -#define DMI_AUTHDATA0_DATA_LENGTH 32 -#define DMI_AUTHDATA0_DATA (0xffffffff << DMI_AUTHDATA0_DATA_OFFSET) -#define DMI_AUTHDATA1 0x21 -#define DMI_AUTHDATA1_DATA_OFFSET 0 -#define DMI_AUTHDATA1_DATA_LENGTH 32 -#define DMI_AUTHDATA1_DATA (0xffffffff << DMI_AUTHDATA1_DATA_OFFSET) -#define DMI_SERDATA 0x22 +#define DMI_DATA1 0x11 +#define DMI_DATA2 0x12 +#define DMI_DATA3 0x13 +#define DMI_DATA4 0x14 +#define DMI_DATA5 0x15 +#define DMI_DATA6 0x16 +#define DMI_DATA7 0x17 +#define DMI_DATA8 0x18 +#define DMI_DATA9 0x19 +#define DMI_DATA10 0x1a +#define DMI_DATA11 0x1b +#define DMI_SERDATA 0x1c #define DMI_SERDATA_DATA_OFFSET 0 #define DMI_SERDATA_DATA_LENGTH 32 #define DMI_SERDATA_DATA (0xffffffff << DMI_SERDATA_DATA_OFFSET) -#define DMI_SERSTATUS 0x23 +#define DMI_SERSTATUS 0x1d #define DMI_SERSTATUS_SERIALCOUNT_OFFSET 28 #define DMI_SERSTATUS_SERIALCOUNT_LENGTH 4 #define DMI_SERSTATUS_SERIALCOUNT (0xf << DMI_SERSTATUS_SERIALCOUNT_OFFSET) @@ -382,6 +379,25 @@ #define DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET 0 #define DMI_SERSTATUS_FULL_OVERFLOW0_LENGTH 1 #define DMI_SERSTATUS_FULL_OVERFLOW0 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET) +#define DMI_ACCESSCS 0x1f +#define DMI_ACCESSCS_PROGSIZE_OFFSET 0 +#define DMI_ACCESSCS_PROGSIZE_LENGTH 4 +#define DMI_ACCESSCS_PROGSIZE (0xf << DMI_ACCESSCS_PROGSIZE_OFFSET) +#define DMI_IBUF0 0x20 +#define DMI_IBUF0_DATA_OFFSET 0 +#define DMI_IBUF0_DATA_LENGTH 32 +#define DMI_IBUF0_DATA (0xffffffff << DMI_IBUF0_DATA_OFFSET) +#define DMI_IBUF1 0x21 +#define DMI_IBUF2 0x22 +#define DMI_IBUF3 0x23 +#define DMI_IBUF4 0x24 +#define DMI_IBUF5 0x25 +#define DMI_IBUF6 0x26 +#define DMI_IBUF7 0x27 +#define DMI_IBUF8 0x28 +#define DMI_IBUF9 0x29 +#define DMI_IBUF10 0x2a +#define DMI_IBUF11 0x2b #define SERINFO 0x110 #define SERINFO_SERIAL7_OFFSET 7 #define SERINFO_SERIAL7_LENGTH 1 diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index b8954e9..e9619c4 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -15,9 +15,22 @@ debug_module_t::debug_module_t(sim_t *sim) : sim(sim) { + dmcontrol = {0}; dmcontrol.version = 1; - write32(debug_rom_entry, 0, jal(0, 0)); + for (unsigned i = 0; i < 1024; i++) { + write32(debug_rom_entry, i, jal(0, 0)); + halted[i] = false; + } + + for (unsigned i = 0; i < datacount; i++) { + data[i] = 0; + } + + for (unsigned i = 0; i < progsize; i++) { + ibuf[i] = 0; + } + } void debug_module_t::reset() @@ -44,6 +57,7 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) addr = DEBUG_START + addr; if (addr >= DEBUG_ROM_ENTRY && addr <= DEBUG_ROM_CODE) { + halted[(addr - DEBUG_ROM_ENTRY) / 4] = true; memcpy(bytes, debug_rom_entry + addr - DEBUG_ROM_ENTRY, len); return true; } @@ -114,7 +128,7 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) { processor_t *proc = current_proc(); if (proc) { - if (proc->halted()) { + if (halted[dmcontrol.hartsel]) { dmcontrol.hartstatus = dmcontrol.HARTSTATUS_HALTED; } else { dmcontrol.hartstatus = dmcontrol.HARTSTATUS_RUNNING; diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 934463f..5fae6a5 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -70,6 +70,7 @@ class debug_module_t : public abstract_device_t // Track which halt notifications from debugger to module are set. std::set<uint32_t> halt_notification; uint8_t debug_rom_entry[1024 * 4]; + bool halted[1024]; void write32(uint8_t *rom, unsigned int index, uint32_t value); uint32_t read32(uint8_t *rom, unsigned int index); diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc index 2605001..3750f9d 100644 --- a/riscv/jtag_dtm.cc +++ b/riscv/jtag_dtm.cc @@ -39,6 +39,7 @@ enum { jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) : dm(dm), + _tck(false), _tms(false), _tdi(false), _tdo(false), dtmcontrol((abits << DTM_DTMCONTROL_ABITS_OFFSET) | 1), dbus(DBUS_OP_STATUS_FAILED << DTM_DBUS_OP_OFFSET), state(TEST_LOGIC_RESET) diff --git a/riscv/remote_bitbang.cc b/riscv/remote_bitbang.cc index 648849c..ff89e15 100644 --- a/riscv/remote_bitbang.cc +++ b/riscv/remote_bitbang.cc @@ -57,6 +57,17 @@ remote_bitbang_t::remote_bitbang_t(uint16_t port, jtag_dtm_t *tap) : strerror(errno), errno); abort(); } + + socklen_t addrlen = sizeof(addr); + if (getsockname(socket_fd, (struct sockaddr *) &addr, &addrlen) == -1) { + fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + printf("Listening for remote bitbang connection on port %d.\n", + ntohs(addr.sin_port)); + fflush(stdout); } void remote_bitbang_t::accept() @@ -87,8 +98,8 @@ void remote_bitbang_t::tick() void remote_bitbang_t::execute_commands() { const unsigned buf_size = 64 * 1024; - char recv_buf[buf_size]; - char send_buf[buf_size]; + static char recv_buf[buf_size]; + static char send_buf[buf_size]; unsigned total_received = 0; ssize_t bytes = read(client_fd, recv_buf, buf_size); bool quit = false; |