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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-11 18:55:09 -0700 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-11 18:55:09 -0700 |
commit | f23ae8b0bcf325de2d691ca5ab1856c5cc32f57b (patch) | |
tree | 8e837fdb6ed938eec35212ec82d8b70fa965ac16 /riscv | |
parent | d6fd350f0c3c0af1760748b358534feb3defcc21 (diff) | |
download | spike-f23ae8b0bcf325de2d691ca5ab1856c5cc32f57b.zip spike-f23ae8b0bcf325de2d691ca5ab1856c5cc32f57b.tar.gz spike-f23ae8b0bcf325de2d691ca5ab1856c5cc32f57b.tar.bz2 |
[xcc] tlb now stores host addresses
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/mmu.cc | 6 | ||||
-rw-r--r-- | riscv/mmu.h | 32 |
2 files changed, 19 insertions, 19 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 05db18f..7ff937d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -27,7 +27,7 @@ void mmu_t::flush_icache() memset(icache_tag, -1, sizeof(icache_tag)); } -reg_t mmu_t::refill(reg_t addr, bool store, bool fetch) +void* mmu_t::refill(reg_t addr, bool store, bool fetch) { reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES; reg_t expected_tag = addr & ~(PGSIZE-1); @@ -51,9 +51,9 @@ reg_t mmu_t::refill(reg_t addr, bool store, bool fetch) tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1; tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1; tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1; - tlb_data[idx] = pte >> PTE_PPN_SHIFT << PGSHIFT; + tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem; - return (addr & (PGSIZE-1)) | tlb_data[idx]; + return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]); } pte_t mmu_t::walk(reg_t addr) diff --git a/riscv/mmu.h b/riscv/mmu.h index d5e144b..ef54079 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -51,9 +51,9 @@ public: badvaddr = addr; \ throw trap_load_address_misaligned; \ } \ - addr = translate(addr, false, false); \ - dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), false); \ - return *(type##_t*)(mem+addr); \ + void* paddr = translate(addr, false, false); \ + dcsim_tick(dcsim, dtlbsim, paddr-mem, sizeof(type##_t), false); \ + return *(type##_t*)paddr; \ } #define store_func(type) \ @@ -63,9 +63,9 @@ public: badvaddr = addr; \ throw trap_store_address_misaligned; \ } \ - addr = translate(addr, true, false); \ - dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), true); \ - *(type##_t*)(mem+addr) = val; \ + void* paddr = translate(addr, true, false); \ + dcsim_tick(dcsim, dtlbsim, paddr-mem, sizeof(type##_t), true); \ + *(type##_t*)paddr = val; \ } insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc) @@ -75,13 +75,13 @@ public: #ifdef RISCV_ENABLE_RVC if(addr % 4 == 2 && rvc) // fetch across word boundary { - reg_t paddr_lo = translate(addr, false, true); - insn.bits = *(uint16_t*)(mem+paddr_lo); + void* addr_lo = translate(addr, false, true); + insn.bits = *(uint16_t*)addr_lo; if(!INSN_IS_RVC(insn.bits)) { - reg_t paddr_hi = translate(addr+2, false, true); - insn.bits |= (uint32_t)*(uint16_t*)(mem+paddr_hi) << 16; + void* addr_hi = translate(addr+2, false, true); + insn.bits |= (uint32_t)*(uint16_t*)addr_hi << 16; } } else @@ -93,8 +93,8 @@ public: return icache_data[idx]; // the processor guarantees alignment based upon rvc mode - reg_t paddr = translate(addr, false, true); - insn = *(insn_t*)(mem+paddr); + void* paddr = translate(addr, false, true); + insn = *(insn_t*)paddr; icache_tag[idx] = addr; icache_data[idx] = insn; @@ -150,7 +150,7 @@ private: bool vm_enabled; static const reg_t TLB_ENTRIES = 256; - pte_t tlb_data[TLB_ENTRIES]; + long tlb_data[TLB_ENTRIES]; reg_t tlb_insn_tag[TLB_ENTRIES]; reg_t tlb_load_tag[TLB_ENTRIES]; reg_t tlb_store_tag[TLB_ENTRIES]; @@ -164,17 +164,17 @@ private: icsim_t* itlbsim; icsim_t* dtlbsim; - reg_t refill(reg_t addr, bool store, bool fetch); + void* refill(reg_t addr, bool store, bool fetch); pte_t walk(reg_t addr); - reg_t translate(reg_t addr, bool store, bool fetch) + void* translate(reg_t addr, bool store, bool fetch) { reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES; reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag; reg_t expected_tag = addr & ~(PGSIZE-1); if(likely(tlb_tag[idx] == expected_tag)) - return (addr & (PGSIZE-1)) | tlb_data[idx]; + return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]); return refill(addr, store, fetch); } |