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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-25 23:01:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-25 23:03:16 -0700 |
| commit | e5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf (patch) | |
| tree | eeac812d700ab4f0e08d6e4ce0a99ae4137c587f /riscv | |
| parent | 6c965e11dc7950207f7cc0baff0ff273c33f4ecc (diff) | |
| download | spike-e5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf.zip spike-e5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf.tar.gz spike-e5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf.tar.bz2 | |
Update state.pc on every instruction
This isn't a bug fix for Spike proper, but it makes it possible for
RoCC instructions to access the control thread's PC.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index c2d5275..0ff5578 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -193,7 +193,7 @@ void processor_t::step(size_t n) { insn_fetch_t fetch = mmu->load_insn(pc); disasm(fetch.insn); - pc = execute_insn(this, pc, fetch); + state.pc = pc = execute_insn(this, pc, fetch); } } else while (instret < n) @@ -204,7 +204,7 @@ void processor_t::step(size_t n) #define ICACHE_ACCESS(idx) { \ insn_fetch_t fetch = ic_entry->data; \ ic_entry++; \ - pc = execute_insn(this, pc, fetch); \ + state.pc = pc = execute_insn(this, pc, fetch); \ instret++; \ if (idx == mmu_t::ICACHE_ENTRIES-1) break; \ if (unlikely(ic_entry->tag != pc)) break; \ @@ -217,11 +217,10 @@ void processor_t::step(size_t n) } catch(trap_t& t) { - pc = take_trap(t, pc); + state.pc = take_trap(t, pc); } catch(serialize_t& s) {} - state.pc = pc; update_timer(&state, instret); } |