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authorAndrew Waterman <andrew@sifive.com>2022-09-22 18:35:12 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-04 15:40:27 -0700
commite2139a5d1c11954ede663539c8666e8696474c01 (patch)
treec72b29369da9ba366a5b83c09cb183214011bdb5 /riscv
parentd2f34d1e41a7d2884aec4d1d3daa1dbf549d059e (diff)
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Suppress unused-variable warnings in vector instruction definitions
Diffstat (limited to 'riscv')
-rw-r--r--riscv/insns/vcpop_m.h2
-rw-r--r--riscv/insns/vfirst_m.h2
-rw-r--r--riscv/insns/vid_v.h3
-rw-r--r--riscv/insns/viota_m.h1
-rw-r--r--riscv/insns/vmv_x_s.h1
-rw-r--r--riscv/insns/vmvnfr_v.h1
6 files changed, 0 insertions, 10 deletions
diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h
index cbe45a4..671362f 100644
--- a/riscv/insns/vcpop_m.h
+++ b/riscv/insns/vcpop_m.h
@@ -2,8 +2,6 @@
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl->read();
-reg_t sew = P.VU.vsew;
-reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();
require(P.VU.vstart->read() == 0);
reg_t popcount = 0;
diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h
index 5b768ed..9ddc82b 100644
--- a/riscv/insns/vfirst_m.h
+++ b/riscv/insns/vfirst_m.h
@@ -2,8 +2,6 @@
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl->read();
-reg_t sew = P.VU.vsew;
-reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();
require(P.VU.vstart->read() == 0);
reg_t pos = -1;
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index c316291..510132d 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -1,11 +1,8 @@
// vmpopc rd, vs2, vm
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
-reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
-reg_t rs1_num = insn.rs1();
-reg_t rs2_num = insn.rs2();
require_align(rd_num, P.VU.vflmul);
require_vm;
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index f74f2c2..1ee9229 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -4,7 +4,6 @@ require_vector(true);
reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
-reg_t rs1_num = insn.rs1();
reg_t rs2_num = insn.rs2();
require(P.VU.vstart->read() == 0);
require_vm;
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h
index 16153eb..57a9e1a 100644
--- a/riscv/insns/vmv_x_s.h
+++ b/riscv/insns/vmv_x_s.h
@@ -1,7 +1,6 @@
// vmv_x_s: rd = vs2[0]
require_vector(true);
require(insn.v_vm() == 1);
-reg_t rs1 = RS1;
reg_t sew = P.VU.vsew;
reg_t rs2_num = insn.rs2();
reg_t res;
diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h
index 543ac58..9c52810 100644
--- a/riscv/insns/vmvnfr_v.h
+++ b/riscv/insns/vmvnfr_v.h
@@ -1,6 +1,5 @@
// vmv<nf>r.v vd, vs2
require_vector(true);
-const reg_t baseAddr = RS1;
const reg_t vd = insn.rd();
const reg_t vs2 = insn.rs2();
const reg_t len = insn.rs1() + 1;