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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-25 21:33:49 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-31 00:44:35 -0700 |
| commit | c9da2943328acf74f58812f1bf29cfc4091dc4cd (patch) | |
| tree | 195c92e357786fa97d62326332eeb209cce7bda2 /riscv | |
| parent | eceda60356a435dfac2c5573badf0144f4c7f146 (diff) | |
| download | spike-c9da2943328acf74f58812f1bf29cfc4091dc4cd.zip spike-c9da2943328acf74f58812f1bf29cfc4091dc4cd.tar.gz spike-c9da2943328acf74f58812f1bf29cfc4091dc4cd.tar.bz2 | |
rvv: add reciprocal instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/encoding.h | 6 | ||||
| -rw-r--r-- | riscv/insns/vfrece7_v.h | 11 | ||||
| -rw-r--r-- | riscv/insns/vfrsqrte7_v.h | 11 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
4 files changed, 30 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 380b660..68801b0 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1306,6 +1306,10 @@ #define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x4c001057 #define MASK_VFSQRT_V 0xfc0ff07f +#define MATCH_VFRSQRTE7_V 0x4c021057 +#define MASK_VFRSQRTE7_V 0xfc0ff07f +#define MATCH_VFRECE7_V 0x4c029057 +#define MASK_VFRECE7_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x4c081057 #define MASK_VFCLASS_V 0xfc0ff07f #define MATCH_VFWADD_VV 0xc0001057 @@ -2648,6 +2652,8 @@ DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) +DECLARE_INSN(vfrsqrte7_v, MATCH_VFRSQRTE7_V, MASK_VFRSQRTE7_V) +DECLARE_INSN(vfrece7_v, MATCH_VFRECE7_V, MASK_VFRECE7_V) DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) diff --git a/riscv/insns/vfrece7_v.h b/riscv/insns/vfrece7_v.h new file mode 100644 index 0000000..69c026b --- /dev/null +++ b/riscv/insns/vfrece7_v.h @@ -0,0 +1,11 @@ +// vfclass.v vd, vs2, vm +VI_VFP_V_LOOP +({ + vd = f16_recip7(vs2); +}, +{ + vd = f32_recip7(vs2); +}, +{ + vd = f64_recip7(vs2); +}) diff --git a/riscv/insns/vfrsqrte7_v.h b/riscv/insns/vfrsqrte7_v.h new file mode 100644 index 0000000..a073764 --- /dev/null +++ b/riscv/insns/vfrsqrte7_v.h @@ -0,0 +1,11 @@ +// vfclass.v vd, vs2, vm +VI_VFP_V_LOOP +({ + vd = f16_rsqrte7(vs2); +}, +{ + vd = f32_rsqrte7(vs2); +}, +{ + vd = f64_rsqrte7(vs2); +}) diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index da50b94..a76809f 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -598,7 +598,9 @@ riscv_insn_ext_v_alu_fp = \ vfredmin_vs \ vfredosum_vs \ vfredsum_vs \ + vfrece7_v \ vfrsub_vf \ + vfrsqrte7_v \ vfsgnj_vf \ vfsgnj_vv \ vfsgnjn_vf \ |