Check vtype.vill for all vector instructions except vsetvl[i]

24 files changed, 37 insertions, 20 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 087be2d..9e03676 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -216,6 +216,10 @@ private:
 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
 
+#define require_vector_vs do { } while (0) // TODO MSTATUS_VS
+#define require_vector do { require_vector_vs; require(!P.VU.vill); } while (0)
+#define require_vector_for_vsetvl do { require_vector_vs; require_extension('V'); } while (0)
+
 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
                                dirty_fp_state; \
                                STATE.fflags |= softfloat_exceptionFlags; \
@@ -378,7 +382,7 @@ static inline bool is_overlaped(const int astart, const int asize,
   require(insn.rs2() + P.VU.vlmul * 2 <= 32);
 
 #define VI_WIDE_CHECK_COMMON \
-  require(!P.VU.vill);\
+  require_vector;\
   require(P.VU.vlmul <= 4); \
   require(P.VU.vsew * 2 <= P.VU.ELEN); \
   require(insn.rd() + P.VU.vlmul * 2 <= 32); \
@@ -411,7 +415,7 @@ static inline bool is_overlaped(const int astart, const int asize,
 //
 #define VI_GENERAL_LOOP_BASE \
   require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t sew = P.VU.vsew; \
   reg_t rd_num = insn.rd(); \
@@ -472,7 +476,7 @@ static inline bool is_overlaped(const int astart, const int asize,
 
 #define VI_LOOP_CMP_BASE \
   require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t sew = P.VU.vsew; \
   reg_t rd_num = insn.rd(); \
@@ -763,7 +767,7 @@ static inline bool is_overlaped(const int astart, const int asize,
 // reduction loop - signed
 #define VI_LOOP_REDUCTION_BASE(x) \
   require(x == e8 || x == e16 || x == e32 || x == e64); \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t rd_num = insn.rd(); \
   reg_t rs1_num = insn.rs1(); \
@@ -1236,7 +1240,7 @@ VI_LOOP_END
   VI_LOOP_REDUCTION_END(sew2)
 
 #define VI_VV_LOOP_WIDE_REDUCTION(BODY) \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t sew = P.VU.vsew; \
   if (sew == e8){ \
     WIDE_REDUCTION_LOOP(e8, e16, BODY) \
@@ -1265,7 +1269,7 @@ VI_LOOP_END
   VI_LOOP_REDUCTION_END(sew2)
 
 #define VI_VV_ULOOP_WIDE_REDUCTION(BODY) \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t sew = P.VU.vsew; \
   if (sew == e8){ \
     WIDE_REDUCTION_ULOOP(e8, e16, BODY) \
@@ -1386,6 +1390,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
 
 #define VI_ST(stride, offset, st_width, elt_byte) \
   const reg_t nf = insn.v_nf() + 1; \
+  require_vector; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
   const reg_t vl = P.VU.vl; \
   const reg_t baseAddr = RS1; \
@@ -1421,6 +1426,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
 
 #define VI_LD(stride, offset, ld_width, elt_byte) \
   const reg_t nf = insn.v_nf() + 1; \
+  require_vector; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
   const reg_t vl = P.VU.vl; \
   const reg_t baseAddr = RS1; \
@@ -1456,6 +1462,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
 
 
 #define VI_LDST_FF(itype, tsew) \
+  require_vector; \
   require(p->VU.vsew >= e##tsew && p->VU.vsew <= e64); \
   const reg_t nf = insn.v_nf() + 1; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
@@ -1510,7 +1517,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   require_extension('F'); \
   require_fp; \
   require(P.VU.vsew == 32); \
-  require(!P.VU.vill);\
+  require_vector;\
   reg_t vl = P.VU.vl; \
   reg_t rd_num = insn.rd(); \
   reg_t rs1_num = insn.rs1(); \
diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index 2e0784c..b056b0e 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -1,6 +1,6 @@
 // vcompress vd, vs2, vs1
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 require(P.VU.vstart == 0);
 reg_t sew = P.VU.vsew;
 reg_t vl = P.VU.vl;
diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h
index 8c216c0..40e2f09 100644
--- a/riscv/insns/vfirst_m.h
+++ b/riscv/insns/vfirst_m.h
@@ -1,6 +1,6 @@
 // vmfirst rd, vs2
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vfmerge_vfm.h b/riscv/insns/vfmerge_vfm.h
index 73d6cee..6d12bce 100644
--- a/riscv/insns/vfmerge_vfm.h
+++ b/riscv/insns/vfmerge_vfm.h
@@ -2,7 +2,7 @@
 require_extension('F');
 require_fp;
 require(P.VU.vsew == 32);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h
index 1444e38..c6dbaff 100644
--- a/riscv/insns/vfmv_f_s.h
+++ b/riscv/insns/vfmv_f_s.h
@@ -1,4 +1,5 @@
 // vfmv_f_s: rd = vs2[0] (rs1=0)
+require_vector;
 require(insn.v_vm() == 1);
 require_fp;
 require_extension('F');
diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h
index 4d1ec2d..cb81008 100644
--- a/riscv/insns/vfmv_s_f.h
+++ b/riscv/insns/vfmv_s_f.h
@@ -1,4 +1,5 @@
 // vfmv_s_f: vd[0] = rs1 (vs2=0)
+require_vector;
 require(insn.v_vm() == 1);
 require_fp;
 require_extension('F');
diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h
index 5b4fb2b..c85a3e9 100644
--- a/riscv/insns/vfmv_v_f.h
+++ b/riscv/insns/vfmv_v_f.h
@@ -2,7 +2,7 @@
 require_extension('F');
 require_fp;
 require(P.VU.vsew == 32);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index ac111d0..df6dd04 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -1,6 +1,6 @@
 // vmpopc rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index c7b831a..fde0291 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -1,6 +1,6 @@
 // vmpopc rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h
index 4fae43a..ec2777a 100644
--- a/riscv/insns/vleff_v.h
+++ b/riscv/insns/vleff_v.h
@@ -1,3 +1,4 @@
+require_vector;
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
 const reg_t nf = insn.v_nf() + 1;
 require((nf * P.VU.vlmul) <= (NVPR / 4));
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index a014900..3047cca 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -1,6 +1,6 @@
 // vmsbf.m vd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index 144b67c..826e7cd 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -1,6 +1,6 @@
 // vmpopc rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index b4cbbce..48805f7 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -1,6 +1,6 @@
 // vmsof.m rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index 1c4ffb2..38b2697 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -1,4 +1,5 @@
 // vmv_s_x: vd[0] = rs1
+require_vector;
 require(insn.v_vm() == 1);
 require(P.VU.vsew == e8 || P.VU.vsew == e16 ||
         P.VU.vsew == e32 || P.VU.vsew == e64);
diff --git a/riscv/insns/vpopc_m.h b/riscv/insns/vpopc_m.h
index 9e22b2b..de50943 100644
--- a/riscv/insns/vpopc_m.h
+++ b/riscv/insns/vpopc_m.h
@@ -1,6 +1,6 @@
 // vmpopc rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h
index a9be102..eff67b8 100644
--- a/riscv/insns/vrgather_vi.h
+++ b/riscv/insns/vrgather_vi.h
@@ -1,6 +1,6 @@
 // vrgather.vi vd, vs2, zimm5 vm # vd[i] = (zimm5 >= VLMAX) ? 0 : vs2[zimm5];
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h
index da8dc81..ce0c2a6 100644
--- a/riscv/insns/vrgather_vv.h
+++ b/riscv/insns/vrgather_vv.h
@@ -1,6 +1,6 @@
 // vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h
index d6c2e38..e9ff3b1 100644
--- a/riscv/insns/vrgather_vx.h
+++ b/riscv/insns/vrgather_vx.h
@@ -1,6 +1,6 @@
 // vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1];
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require(!P.VU.vill);
+require_vector;
 reg_t vl = P.VU.vl;
 reg_t sew = P.VU.vsew;
 reg_t rd_num = insn.rd();
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h
index 773b984..4b1f2e8 100644
--- a/riscv/insns/vsetvl.h
+++ b/riscv/insns/vsetvl.h
@@ -1 +1,2 @@
+require_vector_for_vsetvl;
 WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, RS2));
diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h
index fc5d1ba..7772bc1 100644
--- a/riscv/insns/vsetvli.h
+++ b/riscv/insns/vsetvli.h
@@ -1 +1,2 @@
+require_vector_for_vsetvl;
 WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, insn.v_zimm11()));
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index 9c78154..cf928f8 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -1,4 +1,5 @@
 // vsuxb.v and vsxseg[2-8]b.v
+require_vector;
 require(P.VU.vsew >= e8);
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index 940d8ad..8bd7545 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -1,4 +1,5 @@
 // vsxe.v and vsxseg[2-8]e.v
+require_vector;
 const reg_t sew = P.VU.vsew;
 const reg_t vl = P.VU.vl;
 require(sew >= e8 && sew <= e64);
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index a5113b7..1d5a1bd 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -1,4 +1,5 @@
 // vsxh.v and vsxseg[2-8]h.v
+require_vector;
 require(P.VU.vsew >= e16);
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index 5320156..ec1a8fe 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -1,4 +1,5 @@
 // vsxw.v and vsxseg[2-8]w.v
+require_vector;
 require(P.VU.vsew >= e32);
 reg_t vl = P.VU.vl;
 reg_t baseAddr = RS1;