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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-03-13 16:32:41 -0700 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-13 18:32:41 -0500 |
commit | bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86 (patch) | |
tree | fbbafd65ba485677af7d3bc4352f5dc9b4ff95b3 /riscv | |
parent | 64947480de005d94fb979260eff5751ca5b7d88d (diff) | |
download | spike-bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86.zip spike-bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86.tar.gz spike-bdd229b9ea9a78f2fe5d4af1d0a49cf50484aa86.tar.bz2 |
Move processor.isa to state.misa, since it really belongs there.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/processor.cc | 16 | ||||
-rw-r--r-- | riscv/processor.h | 4 |
2 files changed, 10 insertions, 10 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index ce04044..2500c2b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -64,10 +64,10 @@ void processor_t::parse_isa_string(const char* str) const char* all_subsets = "imafdqc"; max_xlen = 64; - isa = reg_t(2) << 62; + state.misa = reg_t(2) << 62; if (strncmp(p, "rv32", 4) == 0) - max_xlen = 32, isa = reg_t(1) << 30, p += 4; + max_xlen = 32, state.misa = reg_t(1) << 30, p += 4; else if (strncmp(p, "rv64", 4) == 0) p += 4; else if (strncmp(p, "rv", 2) == 0) @@ -83,11 +83,11 @@ void processor_t::parse_isa_string(const char* str) } isa_string = "rv" + std::to_string(max_xlen) + p; - isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode - isa |= 1L << ('u' - 'a'); // advertise support for user mode + state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + state.misa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { - isa |= 1L << (*p - 'a'); + state.misa |= 1L << (*p - 'a'); if (auto next = strchr(all_subsets, *p)) { all_subsets = next + 1; @@ -112,7 +112,7 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && max_xlen < 64) bad_isa_string(str); - max_isa = isa; + max_isa = state.misa; } void state_t::reset() @@ -458,7 +458,7 @@ void processor_t::set_csr(int which, reg_t val) mask |= 1L << ('C' - 'A'); mask &= max_isa; - isa = (val & mask) | (isa & ~mask); + state.misa = (val & mask) | (state.misa & ~mask); break; } case CSR_TSELECT: @@ -607,7 +607,7 @@ reg_t processor_t::get_csr(int which) case CSR_MSCRATCH: return state.mscratch; case CSR_MCAUSE: return state.mcause; case CSR_MTVAL: return state.mtval; - case CSR_MISA: return isa; + case CSR_MISA: return state.misa; case CSR_MARCHID: return 0; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0; diff --git a/riscv/processor.h b/riscv/processor.h index 51fe8d2..7d504d9 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -96,6 +96,7 @@ struct state_t // control and status registers reg_t prv; // TODO: Can this be an enum instead? + reg_t misa; reg_t mstatus; reg_t mepc; reg_t mtval; @@ -185,7 +186,7 @@ public: extension_t* get_extension() { return ext; } bool supports_extension(unsigned char ext) { if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a'; - return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1); + return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1); } void check_pc_alignment(reg_t pc) { if (unlikely(pc & 2) && !supports_extension('C')) @@ -302,7 +303,6 @@ private: uint32_t id; unsigned max_xlen; unsigned xlen; - reg_t isa; reg_t max_isa; std::string isa_string; bool histogram_enabled; |