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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-10 00:03:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-05-10 01:08:15 -0700 |
| commit | b567da9a46367e19768118034dd5757447548556 (patch) | |
| tree | 3fc79d76cb75db1be867cf8f3884f088b62bdd84 /riscv | |
| parent | 43cfe9584638054ae25cc3c952d160277171cc26 (diff) | |
| download | spike-b567da9a46367e19768118034dd5757447548556.zip spike-b567da9a46367e19768118034dd5757447548556.tar.gz spike-b567da9a46367e19768118034dd5757447548556.tar.bz2 | |
Disable PMP checks when configuration includes zero PMP registers
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 6d0b39a..3b0eb0d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -200,7 +200,7 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ reg_t mmu_t::pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode) { - if (!proc) + if (!proc || proc->n_pmp == 0) return true; reg_t base = 0; |