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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-03-19 23:40:38 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-03-19 23:40:38 -0700 |
| commit | b282d6e8c016680e101f50e6b88ea3e505484912 (patch) | |
| tree | 8f523d83a2f89aeac058b8826dc753f1a7956257 /riscv | |
| parent | ccd5c7b1b19600519f45f95a669f61180116b609 (diff) | |
| download | spike-b282d6e8c016680e101f50e6b88ea3e505484912.zip spike-b282d6e8c016680e101f50e6b88ea3e505484912.tar.gz spike-b282d6e8c016680e101f50e6b88ea3e505484912.tar.bz2 | |
make NaN behavior consistent with hardfloat
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/fadd_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fadd_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fmul_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fmul_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fnmadd_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fnmadd_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fnmsub_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fnmsub_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fsub_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fsub_s.h | 2 |
10 files changed, 10 insertions, 10 deletions
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h index 48c76a7..dcc6413 100644 --- a/riscv/insns/fadd_d.h +++ b/riscv/insns/fadd_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_add(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2); set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h index 2fd5429..952d1a7 100644 --- a/riscv/insns/fadd_s.h +++ b/riscv/insns/fadd_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_add(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h index a8adedd..a1462d3 100644 --- a/riscv/insns/fmul_d.h +++ b/riscv/insns/fmul_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mul(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h index 6475578..a954c3d 100644 --- a/riscv/insns/fmul_s.h +++ b/riscv/insns/fmul_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mul(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h index 1e2ee27..9529aeb 100644 --- a/riscv/insns/fnmadd_d.h +++ b/riscv/insns/fnmadd_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN; +FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h index 78abb78..2052b93 100644 --- a/riscv/insns/fnmadd_s.h +++ b/riscv/insns/fnmadd_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN; +FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h index ae643a5..31a5b39 100644 --- a/riscv/insns/fnmsub_d.h +++ b/riscv/insns/fnmsub_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; +FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h index cbb70ba..811a35a 100644 --- a/riscv/insns/fnmsub_s.h +++ b/riscv/insns/fnmsub_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; +FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h index e25eebb..fcabe0e 100644 --- a/riscv/insns/fsub_d.h +++ b/riscv/insns/fsub_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f64_sub(FRS1, FRS2); +FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h index 6c64d04..1ff72d2 100644 --- a/riscv/insns/fsub_s.h +++ b/riscv/insns/fsub_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -FRD = f32_sub(FRS1, FRS2); +FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN); set_fp_exceptions; |