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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-14 18:56:45 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-16 10:52:15 -0700 |
commit | b23d9d5b1d906fd92a160774986ad40851c21020 (patch) | |
tree | afad0ed1cb134ac1e57b43b75be67bf13558c178 /riscv | |
parent | d0a3e776084f3c3d39bba205f6e1304c765c6cc5 (diff) | |
download | spike-b23d9d5b1d906fd92a160774986ad40851c21020.zip spike-b23d9d5b1d906fd92a160774986ad40851c21020.tar.gz spike-b23d9d5b1d906fd92a160774986ad40851c21020.tar.bz2 |
Convert mcycle[h] (which is a mirror of minstret[h]) to csr_t
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/csrs.cc | 15 | ||||
-rw-r--r-- | riscv/csrs.h | 15 | ||||
-rw-r--r-- | riscv/processor.cc | 26 |
3 files changed, 38 insertions, 18 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 082804f..f0f4c68 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -854,3 +854,18 @@ bool minstreth_csr_t::unlogged_write(const reg_t val) noexcept { minstret->write_upper_half(val); return true; } + + +proxy_csr_t::proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): + csr_t(proc, addr), + delegate(delegate) { +} + +reg_t proxy_csr_t::read() const noexcept { + return delegate->read(); +} + +bool proxy_csr_t::unlogged_write(const reg_t val) noexcept { + delegate->write(val); // log only under the original (delegate's) name + return false; +} diff --git a/riscv/csrs.h b/riscv/csrs.h index eeab892..11b13e8 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -447,4 +447,19 @@ class minstreth_csr_t: public csr_t { minstret_csr_t_p minstret; }; +typedef std::shared_ptr<minstreth_csr_t> minstreth_csr_t_p; + + +// For a CSR that is an alias of another +class proxy_csr_t: public csr_t { + public: + proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate); + virtual reg_t read() const noexcept override; + protected: + bool unlogged_write(const reg_t val) noexcept override; + private: + csr_t_p delegate; +}; + + #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index 9bb56d6..22788a8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -377,8 +377,12 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) csrmap[CSR_MTVEC] = mtvec = std::make_shared<tvec_csr_t>(proc, CSR_MTVEC); csrmap[CSR_MCAUSE] = mcause = std::make_shared<cause_csr_t>(proc, CSR_MCAUSE); csrmap[CSR_MINSTRET] = minstret = std::make_shared<minstret_csr_t>(proc, CSR_MINSTRET); - if (xlen == 32) - csrmap[CSR_MINSTRETH] = std::make_shared<minstreth_csr_t>(proc, CSR_MINSTRETH, minstret); + csrmap[CSR_MCYCLE] = std::make_shared<proxy_csr_t>(proc, CSR_MCYCLE, minstret); + if (xlen == 32) { + minstreth_csr_t_p minstreth; + csrmap[CSR_MINSTRETH] = minstreth = std::make_shared<minstreth_csr_t>(proc, CSR_MINSTRETH, minstret); + csrmap[CSR_MCYCLEH] = std::make_shared<proxy_csr_t>(proc, CSR_MCYCLEH, minstreth); + } csrmap[CSR_MIE] = mie = std::make_shared<mie_csr_t>(proc, CSR_MIE); csrmap[CSR_MIP] = mip = std::make_shared<mip_csr_t>(proc, CSR_MIP); auto sip_sie_accr = std::make_shared<generic_int_accessor_t>(this, @@ -974,12 +978,6 @@ void processor_t::set_csr(int which, reg_t val) VU.vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; VU.vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; break; - case CSR_MCYCLE: - state.minstret->write(val); - break; - case CSR_MCYCLEH: - state.minstret->write_upper_half(val); - break; case CSR_MTVAL2: state.mtval2 = val; break; case CSR_MTINST: state.mtinst = val; break; case CSR_HEDELEG: { @@ -1232,13 +1230,9 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) ret(state.minstret->read()); else ret(0); - case CSR_MCYCLE: case CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31: case CSR_MHPMEVENT3 ... CSR_MHPMEVENT31: - if (which == CSR_MCYCLE) - ret(state.minstret->read()); - else - ret(0); + ret(0); case CSR_INSTRETH: case CSR_CYCLEH: case CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H: @@ -1256,13 +1250,9 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) ret(state.minstret->read() >> 32); else ret(0); - case CSR_MCYCLEH: case CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H: if (xlen == 32) { - if (which == CSR_MCYCLEH) - ret(state.minstret->read() >> 32); - else - ret(0); + ret(0); } break; case CSR_MCOUNTINHIBIT: ret(0); |