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author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2021-12-08 11:28:44 +0900 |
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committer | GitHub <noreply@github.com> | 2021-12-07 18:28:44 -0800 |
commit | a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec (patch) | |
tree | 5ce0295f0e44d09ed9c87accc75bd6f4228a0197 /riscv | |
parent | 9b3b305e42d9427618b08c33b5dfe1b5180b9f43 (diff) | |
download | spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.zip spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.tar.gz spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.tar.bz2 |
Add 'Zfhmin' extension (#880)
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating
point) extension, consisting only of data transfer and conversion
instructions.
This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin"
as a multi-letter extension and adjusts feature gate for
data transfer / conversion instructions.
* FLH / FSH
* FMV.X.H / FMV.H.X
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D (if 'D' extension is also present)
* FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/fcvt_d_h.h | 2 | ||||
-rw-r--r-- | riscv/insns/fcvt_h_d.h | 2 | ||||
-rw-r--r-- | riscv/insns/fcvt_h_q.h | 2 | ||||
-rw-r--r-- | riscv/insns/fcvt_h_s.h | 2 | ||||
-rw-r--r-- | riscv/insns/fcvt_q_h.h | 2 | ||||
-rw-r--r-- | riscv/insns/fcvt_s_h.h | 2 | ||||
-rw-r--r-- | riscv/insns/flh.h | 2 | ||||
-rw-r--r-- | riscv/insns/fmv_h_x.h | 2 | ||||
-rw-r--r-- | riscv/insns/fmv_x_h.h | 2 | ||||
-rw-r--r-- | riscv/insns/fsh.h | 2 | ||||
-rw-r--r-- | riscv/processor.cc | 8 | ||||
-rw-r--r-- | riscv/processor.h | 1 |
12 files changed, 16 insertions, 13 deletions
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h index 6906fc0..04e9ff4 100644 --- a/riscv/insns/fcvt_d_h.h +++ b/riscv/insns/fcvt_d_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_extension('D'); require_fp; softfloat_roundingMode = RM; diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h index f463dd5..e9987b7 100644 --- a/riscv/insns/fcvt_h_d.h +++ b/riscv/insns/fcvt_h_d.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_extension('D'); require_fp; softfloat_roundingMode = RM; diff --git a/riscv/insns/fcvt_h_q.h b/riscv/insns/fcvt_h_q.h index 94b0001..4dfdd53 100644 --- a/riscv/insns/fcvt_h_q.h +++ b/riscv/insns/fcvt_h_q.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_extension('Q'); require_fp; softfloat_roundingMode = RM; diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h index eb928e9..ce39d81 100644 --- a/riscv/insns/fcvt_h_s.h +++ b/riscv/insns/fcvt_h_s.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; softfloat_roundingMode = RM; WRITE_FRD(f32_to_f16(f32(FRS1))); diff --git a/riscv/insns/fcvt_q_h.h b/riscv/insns/fcvt_q_h.h index 8a5f680..8bf16ce 100644 --- a/riscv/insns/fcvt_q_h.h +++ b/riscv/insns/fcvt_q_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_extension('Q'); require_fp; softfloat_roundingMode = RM; diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h index bfa2e91..22cdd72 100644 --- a/riscv/insns/fcvt_s_h.h +++ b/riscv/insns/fcvt_s_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; softfloat_roundingMode = RM; WRITE_FRD(f16_to_f32(f16(FRS1))); diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h index c887999..bdb22d3 100644 --- a/riscv/insns/flh.h +++ b/riscv/insns/flh.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; WRITE_FRD(f16(MMU.load_uint16(RS1 + insn.i_imm()))); diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h index c022508..e55d607 100644 --- a/riscv/insns/fmv_h_x.h +++ b/riscv/insns/fmv_h_x.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; WRITE_FRD(f16(RS1)); diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h index 5e89c4f..7a2e5ff 100644 --- a/riscv/insns/fmv_x_h.h +++ b/riscv/insns/fmv_x_h.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; WRITE_RD(sext32((int16_t)(FRS1.v[0]))); diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h index b9fa4e0..9eaae1e 100644 --- a/riscv/insns/fsh.h +++ b/riscv/insns/fsh.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_extension(EXT_ZFHMIN); require_fp; MMU.store_uint16(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/riscv/processor.cc b/riscv/processor.cc index a7b4a5b..e7e60bf 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -250,10 +250,12 @@ void processor_t::parse_isa_string(const char* str) auto end = p; do ++end; while (*end && *end != '_'); auto ext_str = std::string(p, end); - if (ext_str == "zfh") { + if (ext_str == "zfh" || ext_str == "zfhmin") { if (!((max_isa >> ('f' - 'a')) & 1)) - bad_isa_string(str, "'Zfh' extension requires 'F'"); - extension_table[EXT_ZFH] = true; + bad_isa_string(str, ("'" + ext_str + "' extension requires 'F'").c_str()); + extension_table[EXT_ZFHMIN] = true; + if (ext_str == "zfh") + extension_table[EXT_ZFH] = true; } else if (ext_str == "zicsr") { // Spike necessarily has Zicsr, because // Zicsr is implied by the privileged architecture diff --git a/riscv/processor.h b/riscv/processor.h index a7c75f6..c32f624 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -230,6 +230,7 @@ typedef enum { typedef enum { // 65('A') ~ 90('Z') is reserved for standard isa in misa EXT_ZFH, + EXT_ZFHMIN, EXT_ZBA, EXT_ZBB, EXT_ZBC, |