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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-02 19:15:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-02 19:15:42 -0700 |
| commit | 95fafa8f05320a761f70bef022a05c3053ea7b27 (patch) | |
| tree | e955d6a2ee1dc53c6c6b6463ad9ff7c5ce0aaa44 /riscv | |
| parent | 8b389440b7aff4cf7f81dd17babc649abec810b3 (diff) | |
| download | spike-95fafa8f05320a761f70bef022a05c3053ea7b27.zip spike-95fafa8f05320a761f70bef022a05c3053ea7b27.tar.gz spike-95fafa8f05320a761f70bef022a05c3053ea7b27.tar.bz2 | |
Mask medeleg correctly
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 203394b..d23c1ea 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -360,9 +360,13 @@ void processor_t::set_csr(int which, reg_t val) state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { - reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT - | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT - | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT; + reg_t mask = + (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_BREAKPOINT) | + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } |