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author | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:13:38 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:20:02 -0800 |
commit | 94381783d67b8f3faa033058f0361e6a95ce0ecc (patch) | |
tree | edaa8dcd27e05b4ee560cfc242e9f2ddfd1aa05f /riscv | |
parent | 5b7cdbe1cf75112bd2a472b7490b15fa7078d798 (diff) | |
download | spike-94381783d67b8f3faa033058f0361e6a95ce0ecc.zip spike-94381783d67b8f3faa033058f0361e6a95ce0ecc.tar.gz spike-94381783d67b8f3faa033058f0361e6a95ce0ecc.tar.bz2 |
DRY in illegal-instruction descriptors
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/processor.cc | 6 | ||||
-rw-r--r-- | riscv/processor.h | 9 |
2 files changed, 11 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 625159f..6e6252c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1068,7 +1068,7 @@ void processor_t::build_opcode_map() std::sort(instructions.begin(), instructions.end(), cmp()); for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) - opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction}; + opcode_cache[i] = insn_desc_t::illegal(); } void processor_t::register_extension(extension_t* x) @@ -1107,7 +1107,9 @@ void processor_t::register_base_instructions() #include "insn_list.h" #undef DEFINE_INSN - register_insn({0, 0, &illegal_instruction, &illegal_instruction}); + // terminate instruction list with a catch-all + register_insn(insn_desc_t::illegal()); + build_opcode_map(); } diff --git a/riscv/processor.h b/riscv/processor.h index 2d14bb3..de896bf 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -23,6 +23,8 @@ class trap_t; class extension_t; class disassembler_t; +reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); + struct insn_desc_t { insn_bits_t match; @@ -31,6 +33,11 @@ struct insn_desc_t insn_func_t rv64; insn_func_t func(int xlen) { return xlen == 64 ? rv64 : rv32; } + + static insn_desc_t illegal() + { + return {0, 0, &illegal_instruction, &illegal_instruction}; + } }; // regnum, data @@ -596,8 +603,6 @@ public: vectorUnit_t VU; }; -reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); - #define REGISTER_INSN(proc, name, match, mask, archen) \ extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \ |