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authorAndrew Waterman <andrew@sifive.com>2020-09-15 10:08:24 -0700
committerAndrew Waterman <andrew@sifive.com>2020-09-15 10:08:24 -0700
commit8957a8efec78ba7ad59a8719366a14a0674a1ee4 (patch)
treea502cbd02a03e0f70d865493be01947e780a83b1 /riscv
parent58f23e111fcfe317f366e2a77c04bad274f436d2 (diff)
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No need to catch illegal CSRs in set_csr
get_csr is always called first (and this assumption is pervasively relied upon), so the checks in set_csr are redundant. FYI @avpatel
Diffstat (limited to 'riscv')
-rw-r--r--riscv/processor.cc18
1 files changed, 2 insertions, 16 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6cc557f..c20643a 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1010,18 +1010,8 @@ void processor_t::set_csr(int which, reg_t val)
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MTVAL: state.mtval = val; break;
- case CSR_MTVAL2:
- if (supports_extension('H'))
- state.mtval2 = val;
- else
- throw trap_illegal_instruction(0);
- break;
- case CSR_MTINST:
- if (supports_extension('H'))
- state.mtinst = val;
- else
- throw trap_illegal_instruction(0);
- break;
+ case CSR_MTVAL2: state.mtval2 = val; break;
+ case CSR_MTINST: state.mtinst = val; break;
case CSR_MISA: {
// the write is ignored if increasing IALIGN would misalign the PC
if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
@@ -1080,10 +1070,6 @@ void processor_t::set_csr(int which, reg_t val)
state.mie = (state.mie & ~mask) | (val & mask);
break;
}
- case CSR_HTIMEDELTA:
- case CSR_HTIMEDELTAH:
- throw trap_illegal_instruction(0);
- break;
case CSR_HCOUNTEREN:
state.hcounteren = val;
break;