diff options
author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:52:18 -0700 |
---|---|---|
committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:52:27 -0700 |
commit | 88c1bfce90a12f11ab8bc53659535afe618d7f3b (patch) | |
tree | 40429707f4db05d920dafcc92e8b1a083760bf3c /riscv | |
parent | 464a7fb56a9152bc16a7ae5e519a3d21781f02a1 (diff) | |
download | spike-88c1bfce90a12f11ab8bc53659535afe618d7f3b.zip spike-88c1bfce90a12f11ab8bc53659535afe618d7f3b.tar.gz spike-88c1bfce90a12f11ab8bc53659535afe618d7f3b.tar.bz2 |
Convert vl to csr_t
Adds commit log events for vl to many vector instructions.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 34 | ||||
-rw-r--r-- | riscv/execute.cc | 2 | ||||
-rw-r--r-- | riscv/insns/vcpop_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfirst_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfmv_s_f.h | 2 | ||||
-rw-r--r-- | riscv/insns/vid_v.h | 4 | ||||
-rw-r--r-- | riscv/insns/viota_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsbf_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsif_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmsof_m.h | 2 | ||||
-rw-r--r-- | riscv/insns/vmv_s_x.h | 2 | ||||
-rw-r--r-- | riscv/processor.cc | 16 | ||||
-rw-r--r-- | riscv/processor.h | 6 |
13 files changed, 37 insertions, 41 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index e5c67a9..16b84da 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -614,7 +614,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define VI_GENERAL_LOOP_BASE \ require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ require_vector(true);\ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t sew = P.VU.vsew; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ @@ -639,7 +639,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define VI_LOOP_CMP_BASE \ require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ require_vector(true);\ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t sew = P.VU.vsew; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ @@ -658,7 +658,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define VI_LOOP_MASK(op) \ require(P.VU.vsew <= e64); \ require_vector(true);\ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ int midx = i / 64; \ int mpos = i % 64; \ @@ -949,7 +949,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // reduction loop - signed #define VI_LOOP_REDUCTION_BASE(x) \ require(x >= e8 && x <= e64); \ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ @@ -980,7 +980,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // reduction loop - unsgied #define VI_ULOOP_REDUCTION_BASE(x) \ require(x >= e8 && x <= e64); \ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ @@ -1299,7 +1299,7 @@ VI_LOOP_END // wide reduction loop - signed #define VI_LOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ @@ -1327,7 +1327,7 @@ VI_LOOP_END // wide reduction loop - unsigned #define VI_ULOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ @@ -1521,7 +1521,7 @@ VI_LOOP_END #define VI_DUPLICATE_VREG(reg_num, idx_sew) \ reg_t index[P.VU.vlmax]; \ -for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ + for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl->read() != 0; ++i) { \ switch(idx_sew) { \ case e8: \ index[i] = P.VU.elt<uint8_t>(reg_num, i); \ @@ -1540,7 +1540,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ #define VI_LD(stride, offset, elt_width, is_mask_ldst) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ VI_CHECK_LOAD(elt_width, is_mask_ldst); \ @@ -1558,7 +1558,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ #define VI_LD_INDEX(elt_width, is_seg) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = P.VU.vl; \ + const reg_t vl = P.VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ if (!is_seg) \ @@ -1594,7 +1594,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ #define VI_ST(stride, offset, elt_width, is_mask_ldst) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ VI_CHECK_STORE(elt_width, is_mask_ldst); \ @@ -1612,7 +1612,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ #define VI_ST_INDEX(elt_width, is_seg) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = P.VU.vl; \ + const reg_t vl = P.VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ if (!is_seg) \ @@ -1649,7 +1649,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ #define VI_LDST_FF(elt_width) \ const reg_t nf = insn.v_nf() + 1; \ const reg_t sew = p->VU.vsew; \ - const reg_t vl = p->VU.vl; \ + const reg_t vl = p->VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t rd_num = insn.rd(); \ VI_CHECK_LOAD(elt_width, false); \ @@ -1668,7 +1668,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ throw; /* Only take exception on zeroth element */ \ /* Reduce VL if an exception occurs on a later element */ \ early_stop = true; \ - P.VU.vl = i; \ + P.VU.vl->write_raw(i); \ break; \ } \ p->VU.elt<elt_width##_t>(rd_num + fn * emul, vreg_inx, true) = val; \ @@ -1765,7 +1765,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ } \ VI_DUPLICATE_VREG(insn.rs2(), idx_type); \ - const reg_t vl = P.VU.vl; \ + const reg_t vl = P.VU.vl->read(); \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ @@ -1848,7 +1848,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ (P.VU.vsew == e64 && p->extension_enabled('D'))); \ require_vector(true);\ require(STATE.frm->read() < 0x5);\ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ @@ -2264,7 +2264,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ (P.VU.vsew == e16 && p->extension_enabled('F')) || \ (P.VU.vsew == e32 && p->extension_enabled('D'))); \ require(STATE.frm->read() < 0x5);\ - reg_t vl = P.VU.vl; \ + reg_t vl = P.VU.vl->read(); \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ diff --git a/riscv/execute.cc b/riscv/execute.cc index 95471a9..875ce5d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -125,7 +125,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) p->VU.vsew, p->VU.vflmul < 1 ? "mf" : "m", p->VU.vflmul < 1 ? (reg_t)(1 / p->VU.vflmul) : (reg_t)p->VU.vflmul, - p->VU.vl); + p->VU.vl->read()); show_vec = true; } diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h index fb3e620..cbe45a4 100644 --- a/riscv/insns/vcpop_m.h +++ b/riscv/insns/vcpop_m.h @@ -1,7 +1,7 @@ // vmpopc rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h index 71e8379..5b768ed 100644 --- a/riscv/insns/vfirst_m.h +++ b/riscv/insns/vfirst_m.h @@ -1,7 +1,7 @@ // vmfirst rd, vs2 require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index 116ed45..edc376e 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -6,7 +6,7 @@ require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZFH)) || (P.VU.vsew == e64 && p->extension_enabled('D'))); require(STATE.frm->read() < 0x5); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index 0b5c89c..c316291 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -1,7 +1,7 @@ // vmpopc rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); @@ -9,7 +9,7 @@ reg_t rs2_num = insn.rs2(); require_align(rd_num, P.VU.vflmul); require_vm; -for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl; ++i) { +for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) { VI_LOOP_ELEMENT_SKIP(); switch (sew) { diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h index 68926e4..f74f2c2 100644 --- a/riscv/insns/viota_m.h +++ b/riscv/insns/viota_m.h @@ -1,7 +1,7 @@ // vmpopc rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 9e32531..6147f6d 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0); require_vm; require(insn.rd() != insn.rs2()); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 8867646..447813f 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0); require_vm; require(insn.rd() != insn.rs2()); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index a2f247f..b9edcf3 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0); require_vm; require(insn.rd() != insn.rs2()); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index cc2d6f0..b66855b 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -2,7 +2,7 @@ require_vector(true); require(insn.v_vm() == 1); require(P.VU.vsew >= e8 && P.VU.vsew <= e64); -reg_t vl = P.VU.vl; +reg_t vl = P.VU.vl->read(); if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); diff --git a/riscv/processor.cc b/riscv/processor.cc index db36199..773ff87 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -556,6 +556,7 @@ void processor_t::vectorUnit_t::reset(){ csrmap[CSR_VXSAT] = vxsat = std::make_shared<vector_csr_t>(p, CSR_VXSAT, /*mask*/ 0x1ul); csrmap[CSR_VSTART] = vstart = std::make_shared<vector_csr_t>(p, CSR_VSTART, /*mask*/ VLEN - 1); csrmap[CSR_VXRM] = vxrm = std::make_shared<vector_csr_t>(p, CSR_VXRM, /*mask*/ 0x3ul); + csrmap[CSR_VL] = vl = std::make_shared<vector_csr_t>(p, CSR_VL, /*mask*/ 0); vtype = 0; set_vl(0, 0, 0, -1); // default to illegal configuration @@ -584,18 +585,18 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT // set vl if (vlmax == 0) { - vl = 0; + vl->write_raw(0); } else if (rd == 0 && rs1 == 0) { - vl = vl > vlmax ? vlmax : vl; + vl->write_raw(vl->read() > vlmax ? vlmax : vl->read()); } else if (rd != 0 && rs1 == 0) { - vl = vlmax; + vl->write_raw(vlmax); } else if (rs1 != 0) { - vl = reqVL > vlmax ? vlmax : reqVL; + vl->write_raw(reqVL > vlmax ? vlmax : reqVL); } vstart->write_raw(0); setvl_count++; - return vl; + return vl->read(); } void processor_t::set_debug(bool value) @@ -1022,11 +1023,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) if (!extension_enabled('V')) break; ret((VU.vxsat->read() << VCSR_VXSAT_SHIFT) | (VU.vxrm->read() << VCSR_VXRM_SHIFT)); - case CSR_VL: - require_vector_vs; - if (!extension_enabled('V')) - break; - ret(VU.vl); case CSR_VTYPE: require_vector_vs; if (!extension_enabled('V')) diff --git a/riscv/processor.h b/riscv/processor.h index 0cc75b3..c4a4243 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -511,8 +511,8 @@ public: char reg_referenced[NVPR]; int setvl_count; reg_t vlmax; - reg_t vl, vtype, vlenb; - vector_csr_t_p vxrm, vstart, vxsat; + reg_t vtype, vlenb; + vector_csr_t_p vxrm, vstart, vxsat, vl; reg_t vma, vta; reg_t vsew; float vflmul; @@ -553,12 +553,12 @@ public: reg_referenced{0}, setvl_count(0), vlmax(0), - vl(0), vtype(0), vlenb(0), vxrm(0), vstart(0), vxsat(0), + vl(0), vma(0), vta(0), vsew(0), |