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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-11 15:19:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-11 15:19:55 -0700 |
| commit | 86d9fe49eda1fff863a43e682015216a25cc72f3 (patch) | |
| tree | 2b08668898ddb0a02ad6c012a0eff200ca55fdc1 /riscv | |
| parent | a3e8585aecaf09eb543e2ade7d7fb2f7c17aea56 (diff) | |
| download | spike-86d9fe49eda1fff863a43e682015216a25cc72f3.zip spike-86d9fe49eda1fff863a43e682015216a25cc72f3.tar.gz spike-86d9fe49eda1fff863a43e682015216a25cc72f3.tar.bz2 | |
Set tval on illegal subforms of aes64ks1i
h/t @YenHaoChen
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/aes64ks1i.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index 3ce3c3f..c7354d6 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,10 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if (enc_rcon > 0xA) { - // Invalid opcode. - throw trap_illegal_instruction(0); -} +require(enc_rcon <= 0xA); uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; |