Move num_triggers knowledge into triggers.h

4 files changed, 8 insertions, 10 deletions

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index aa726d4..6ead297 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -982,7 +982,7 @@ tselect_csr_t::tselect_csr_t(processor_t* const proc, const reg_t addr):
 }
 
 bool tselect_csr_t::unlogged_write(const reg_t val) noexcept {
-  return basic_csr_t::unlogged_write((val < state->num_triggers) ? val : read());
+  return basic_csr_t::unlogged_write((val < proc->TM.count()) ? val : read());
 }
 
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5aae1f2..0543c26 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -29,7 +29,7 @@ processor_t::processor_t(isa_parser_t isa, const char* varch,
   : debug(false), halt_request(HR_NONE), isa(isa), sim(sim), id(id), xlen(0),
   histogram_enabled(false), log_commits_enabled(false),
   log_file(log_file), sout_(sout_.rdbuf()), halt_on_reset(halt_on_reset),
-  impl_table(256, false), last_pc(1), executions(1), TM(state.num_triggers)
+  impl_table(256, false), last_pc(1), executions(1), TM(4)
 {
   VU.p = this;
   TM.proc = this;
@@ -173,8 +173,6 @@ static int xlen_to_uxl(int xlen)
   abort();
 }
 
-const int state_t::num_triggers;
-
 void state_t::reset(processor_t* const proc, reg_t max_isa)
 {
   pc = DEFAULT_RSTVEC;
@@ -997,14 +995,14 @@ void processor_t::trigger_updated()
   mmu->check_triggers_load = false;
   mmu->check_triggers_store = false;
 
-  for (unsigned i = 0; i < state.num_triggers; i++) {
-    if (TM.triggers[i]->execute) {
+  for (auto trigger : TM.triggers) {
+    if (trigger->execute) {
       mmu->check_triggers_fetch = true;
     }
-    if (TM.triggers[i]->load) {
+    if (trigger->load) {
       mmu->check_triggers_load = true;
     }
-    if (TM.triggers[i]->store) {
+    if (trigger->store) {
       mmu->check_triggers_store = true;
     }
   }
diff --git a/riscv/processor.h b/riscv/processor.h
index 776496c..a09b6b6 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -124,8 +124,6 @@ struct state_t
 {
   void reset(processor_t* const proc, reg_t max_isa);
 
-  static const int num_triggers = 4;
-
   reg_t pc;
   regfile_t<reg_t, NXPR, true> XPR;
   regfile_t<freg_t, NFPR, false> FPR;
diff --git a/riscv/triggers.h b/riscv/triggers.h
index bcd4b01..6752807 100644
--- a/riscv/triggers.h
+++ b/riscv/triggers.h
@@ -100,6 +100,8 @@ class module_t {
 public:
   module_t(unsigned count);
 
+  unsigned count() const { return triggers.size(); }
+
   match_result_t memory_access_match(action_t *action,
       operation_t operation, reg_t address, reg_t data);