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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-01 00:44:52 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-04 09:50:05 -0700 |
commit | 817fb0799f2654721bd615cc303a50b05aeb1929 (patch) | |
tree | 69b10746014d125fb4def7c030e7a7c7c40d425a /riscv | |
parent | 2b38341691cae78d1e06c9e80af1944d4c7aa0e5 (diff) | |
download | spike-817fb0799f2654721bd615cc303a50b05aeb1929.zip spike-817fb0799f2654721bd615cc303a50b05aeb1929.tar.gz spike-817fb0799f2654721bd615cc303a50b05aeb1929.tar.bz2 |
fp16: add helper macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index be310c3..4f55f5f 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -282,21 +282,29 @@ class wait_for_interrupt_t {}; #define invalid_pc(pc) ((pc) & 1) /* Convenience wrappers to simplify softfloat code sequences */ +#define isBoxedF16(r) (isBoxedF32(r) && ((uint64_t)((r.v[0] >> 16) + 1) == ((uint64_t)1 << 48))) +#define unboxF16(r) (isBoxedF16(r) ? (uint32_t)r.v[0] : defaultNaNF16UI) #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) #define isBoxedF64(r) ((r.v[1] + 1) == 0) #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) typedef float128_t freg_t; +inline float16_t f16(uint16_t v) { return { v }; } inline float32_t f32(uint32_t v) { return { v }; } inline float64_t f64(uint64_t v) { return { v }; } +inline float16_t f16(freg_t r) { return f16(unboxF16(r)); } inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } inline float128_t f128(freg_t r) { return r; } +inline freg_t freg(float16_t f) { return { ((uint64_t)-1 << 16) | f.v, (uint64_t)-1 }; } inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; } inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } inline freg_t freg(float128_t f) { return f; } +#define F16_SIGN ((uint16_t)1 << 15) #define F32_SIGN ((uint32_t)1 << 31) #define F64_SIGN ((uint64_t)1 << 63) +#define fsgnj16(a, b, n, x) \ + f16((f16(a).v & ~F16_SIGN) | ((((x) ? f16(a).v : (n) ? F16_SIGN : 0) ^ f16(b).v) & F16_SIGN)) #define fsgnj32(a, b, n, x) \ f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) #define fsgnj64(a, b, n, x) \ |