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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-20 17:14:15 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-20 17:14:15 -0700 |
| commit | 7c4cf010a10a1ea5ab18e8d65ab9e56a4f8b767e (patch) | |
| tree | 479fd34356d472fe68288c4c42026b050f4850e7 /riscv | |
| parent | 326fa00f587c43f76d94acbeaed83ffba2e07d3b (diff) | |
| parent | dfd191367991cb157b53767dcc05824c826b5abd (diff) | |
| download | spike-7c4cf010a10a1ea5ab18e8d65ab9e56a4f8b767e.zip spike-7c4cf010a10a1ea5ab18e8d65ab9e56a4f8b767e.tar.gz spike-7c4cf010a10a1ea5ab18e8d65ab9e56a4f8b767e.tar.bz2 | |
Merge pull request #1085 from ImanHosseini/patch1
Detect loading isa-incompatible code
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/sim.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 0000537..0ef13b8 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -202,6 +202,7 @@ int sim_t::run() { host = context_t::current(); target.init(sim_thread_main, this); + htif_t::set_expected_xlen(isa.get_max_xlen()); return htif_t::run(); } |