diff options
author | liweiwei90 <34847211+liweiwei90@users.noreply.github.com> | 2022-08-10 05:50:53 +0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-08-09 14:50:53 -0700 |
commit | 7383118078a98112ca4036919e6654d8171d2274 (patch) | |
tree | 8e1ce9b95d3781bdca4ce14b8bcbc5a8a6d66530 /riscv | |
parent | c5fc01694d6db6bc275fa97126e3573c5a6b7511 (diff) | |
download | spike-7383118078a98112ca4036919e6654d8171d2274.zip spike-7383118078a98112ca4036919e6654d8171d2274.tar.gz spike-7383118078a98112ca4036919e6654d8171d2274.tar.bz2 |
Fix exception type for accessing (v)stimecmp (#1061)
Illegal instruciton trap should be raised when accessing if related
bit of mcounteren.TM or menvcfg.STCE is zero in VS/VU mode
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/csrs.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7de49a7..bc5db50 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1411,17 +1411,18 @@ virtualized_stimecmp_csr_t::virtualized_stimecmp_csr_t(processor_t* const proc, } void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const { - virtualized_csr_t::verify_permissions(insn, write); - - // check for read permission to time as enabled by xcounteren - state->time_proxy->verify_permissions(insn, false); - if (!(state->menvcfg->read() & MENVCFG_STCE)) { // access to (v)stimecmp with MENVCFG.STCE = 0 if (state->prv < PRV_M) throw trap_illegal_instruction(insn.bits()); - } else if (state->v && !(state->henvcfg->read() & HENVCFG_STCE)) { + } + + state->time_proxy->verify_permissions(insn, false); + + if (state->v && !(state->henvcfg->read() & HENVCFG_STCE)) { // access to vstimecmp with MENVCFG.STCE = 1 and HENVCFG.STCE = 0 when V = 1 throw trap_virtual_instruction(insn.bits()); } + + virtualized_csr_t::verify_permissions(insn, write); } |