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author | Tim Newsome <tim@sifive.com> | 2022-05-02 09:26:46 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-05-02 13:15:18 -0700 |
commit | 62ecca6f8a8fdceb0e2bf54bc21ea5899e100ea8 (patch) | |
tree | 02842cf617ece4863af97005ccf5d8666b949101 /riscv | |
parent | 85fbd75d44c369ccb358d70bb4adc3a82a23c495 (diff) | |
download | spike-62ecca6f8a8fdceb0e2bf54bc21ea5899e100ea8.zip spike-62ecca6f8a8fdceb0e2bf54bc21ea5899e100ea8.tar.gz spike-62ecca6f8a8fdceb0e2bf54bc21ea5899e100ea8.tar.bz2 |
Use MCONTROL_TYPE_MATCH macro instead of 2
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index ed9105e..4d16a58 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -14,7 +14,7 @@ mcontrol_t::mcontrol_t() : reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { reg_t v = 0; auto xlen = proc->get_xlen(); - v = set_field(v, MCONTROL_TYPE(xlen), 2); + v = set_field(v, MCONTROL_TYPE(xlen), MCONTROL_TYPE_MATCH); v = set_field(v, MCONTROL_DMODE(xlen), dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), 0); v = set_field(v, CSR_MCONTROL_HIT, hit); |