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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-20 01:48:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-20 01:48:58 -0700 |
| commit | 59a9277ac1e3f9aca630fb035d1dbacaa091e375 (patch) | |
| tree | c31c933c69e5e3217d88333f4d4fe2c7143ad078 /riscv | |
| parent | f3055afa55125627be0b64bf7b8bd1c876d9bc79 (diff) | |
| download | spike-59a9277ac1e3f9aca630fb035d1dbacaa091e375.zip spike-59a9277ac1e3f9aca630fb035d1dbacaa091e375.tar.gz spike-59a9277ac1e3f9aca630fb035d1dbacaa091e375.tar.bz2 | |
ebreak should write mtval with 0, not pc
Resolves #426
The relevant passage in the spec does not mention software breakpoints
as one of the cases that cause mtval to be set to a nonzero value:
https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/c_ebreak.h | 2 | ||||
| -rw-r--r-- | riscv/insns/ebreak.h | 2 | ||||
| -rw-r--r-- | riscv/trap.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h index 128b86b..a17200f 100644 --- a/riscv/insns/c_ebreak.h +++ b/riscv/insns/c_ebreak.h @@ -1,2 +1,2 @@ require_extension('C'); -throw trap_breakpoint(pc); +throw trap_breakpoint(); diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h index 736cebe..c22776c 100644 --- a/riscv/insns/ebreak.h +++ b/riscv/insns/ebreak.h @@ -1 +1 @@ -throw trap_breakpoint(pc); +throw trap_breakpoint(); diff --git a/riscv/trap.h b/riscv/trap.h index b5b8a50..ac048eb 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -47,7 +47,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) -DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) |